]> Joshua Wise's Git repositories - firearm.git/blame - BlockRAM.v
Only emit a stall if we didn't take a bubble in.
[firearm.git] / BlockRAM.v
CommitLineData
2f8f0594
JW
1module BlockRAM(
2 input clk,
3 input [31:0] bus_addr,
4 output wire [31:0] bus_rdata,
5 input [31:0] bus_wdata,
6 input bus_rd,
7 input bus_wr,
8 output wire bus_ready
9 );
10
11 /* This module is mapped in physical memory from 0x00000000 to
12 * 0x00004000. rdata and ready must be driven to zero if the
13 * address is not within the range of this module.
14 */
45fa96c0
JW
15 wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
16 /* verilator lint_off WIDTH */
17 wire [13:2] ramaddr = bus_addr & 32'h3FFC; /* mask off lower two bits
18 * for word alignment */
19 /* verilator lint_on WIDTH */
2f8f0594
JW
20
21 reg [31:0] data [0:(16384 / 4 - 1)];
22
23 reg [31:0] temprdata;
24 reg [13:2] lastread;
25 assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
26
27 assign bus_ready = decode &&
28 (bus_wr || (bus_rd && (lastread == ramaddr)));
29
30 always @(posedge clk)
31 begin
32 if (bus_wr && decode)
33 data[ramaddr] <= bus_wdata;
34
35 /* This is not allowed to be conditional -- stupid Xilinx
36 * blockram. */
37 temprdata <= data[ramaddr];
38 lastread <= ramaddr;
39 end
40endmodule
This page took 0.029122 seconds and 4 git commands to generate.