DCache/ICache: reg i -> integer i
[firearm.git] / Fetch.v
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1module Fetch(
2 input clk,
3 input Nrst,
4
5 output wire [31:0] rd_addr,
6 output wire rd_req,
7 input rd_wait,
8 input [31:0] rd_data,
9
10 input stall,
11 input jmp,
45fa96c0 12 input [31:0] jmppc,
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13 output reg bubble = 1,
14 output reg [31:0] insn = 0,
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15 output reg [31:0] pc = 32'hFFFFFFFC);
16
ac3ae95a 17 reg qjmp = 0; /* A jump has been queued up while we were waiting. */
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18 reg [31:0] qjmppc;
19 always @(posedge clk)
ae185fc4 20 if ((rd_wait || stall) && jmp && !qjmp)
6318a7e8 21 {qjmp,qjmppc} <= {jmp, jmppc};
ae185fc4 22 else if (!rd_wait && !stall && qjmp) /* It has already been intoed. */
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23 {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
24
25 reg [31:0] reqpc;
26 always @(*)
27 if (stall)
28 reqpc = pc;
29 else if (qjmp)
30 reqpc = qjmppc;
bd073175 31 else if (jmp)
6318a7e8 32 reqpc = jmppc;
bd073175 33 else
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34 reqpc = pc + 4;
35
36 assign rd_addr = reqpc;
37 assign rd_req = 1;
38
39 always @(negedge Nrst)
40 begin
41 pc <= 32'hFFFFFFFC;
42 qjmp <= 0;
43 bubble <= 1;
44 end
bd073175 45
bd073175 46 always @(posedge clk)
90ff449a 47 begin
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48 if (!Nrst) begin
49 pc <= 32'hFFFFFFFC;
50 qjmp <= 0;
51 bubble <= 1;
52 end else if (!stall)
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53 begin
54 bubble <= rd_wait;
55 insn <= rd_data;
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56 if (!rd_wait)
57 pc <= reqpc;
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58 end
59 end
bd073175 60endmodule
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