Initial import

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..ef9e12a
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,68 @@
+TARGET = VTerm
+VLOGS = VTerm.v
+VLOGS_ALL = $(VLOGS)
+
+BITGEN_OPTS = \
+       -w \
+       -g DebugBitstream:No \
+       -g Binary:no \
+       -g CRC:Enable \
+       -g ConfigRate:1 \
+       -g ProgPin:PullUp \
+       -g DonePin:PullUp \
+       -g TckPin:PullUp \
+       -g TdiPin:PullUp \
+       -g TdoPin:PullUp \
+       -g TmsPin:PullUp \
+       -g UnusedPin:PullDown \
+       -g UserID:0xFFFFFFFF \
+       -g DCMShutdown:Disable \
+       -g StartUpClk:CClk \
+       -g DONE_cycle:4 \
+       -g GTS_cycle:5 \
+       -g GWE_cycle:6 \
+       -g LCK_cycle:NoWait \
+       -g Security:None \
+       -g DonePipe:No \
+       -g DriveDone:No
+
+all: $(TARGET).svf
+
+$(TARGET).ngc: $(TARGET).xst $(VLOGS_ALL)
+       @mkdir -p xst/projnav.tmp
+       @echo work > $(TARGET).lso
+       @rm -f $(TARGET).prj
+       @for i in $(VLOGS); do echo verilog work '"'$$i'"' >> $(TARGET).prj; done
+       xst -ifn $(TARGET).xst -ofn $(TARGET).syr
+
+$(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf
+       ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc3s500e-fg320-5 "$(TARGET).ngc" $(TARGET).ngd
+
+$(TARGET)_map.ncd: $(TARGET).ngd
+       map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf
+
+$(TARGET).ncd: $(TARGET)_map.ncd
+       par -w -ol std -t 1 $(TARGET)_map.ncd $(TARGET).ncd $(TARGET).pcf
+
+$(TARGET).twr: $(TARGET)_map.ncd
+       trce -e 3 -s 5 -xml $(TARGET) $(TARGET).ncd -o $(TARGET).twr $(TARGET).pcf -ucf $(TARGET).ucf
+
+$(TARGET).bit: $(TARGET).ncd
+       bitgen $(BITGEN_OPTS) $(TARGET).ncd
+
+$(TARGET).svf: $(TARGET).bit impact.cmd
+       sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
+       impact -batch tmp.cmd
+
+clean:
+       rm -f $(TARGET).bgn $(TARGET).ngc $(TARGET).svf $(TARGET).ngd $(TARGET).bit $(TARGET).twr $(TARGET).ncd $(TARGET)_map.ncd $(TARGET)_map.*
+       rm -f $(TARGET).bld $(TARGET).drc $(TARGET)_ngdbuild.xrpt $(TARGET)_pad.* $(TARGET).pad $(TARGET).par $(TARGET)_par.xrpt $(TARGET).ngr
+       rm -f $(TARGET).pcf $(TARGET)_summary.xml $(TARGET).unroutes $(TARGET)_usage.xml $(TARGET)_xst.xrpt $(TARGET).syr $(TARGET).ptwx $(TARGET).xpi
+       rm -rf xst
+       rm -rf xlnx_auto_*
+       rm -rf _ngo
+       rm -f tmp.cmd
+       rm -f _impactbatch.log
+       rm -f $(TARGET).prj
+       rm -f $(TARGET).lso
+

diff --git a/VTerm.ucf b/VTerm.ucf
new file mode 100644 (file)
index 0000000..13e25f9
--- /dev/null
+++ b/VTerm.ucf
@@ -0,0 +1,12 @@
+NET "xtal" LOC="B8" | CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "vs" LOC="u3";
+NET "hs" LOC="t4";
+NET "red<2>" LOC="r8";
+NET "red<1>" LOC="t8";
+NET "red<0>" LOC="r9";
+NET "green<2>" LOC="p6";
+NET "green<1>" LOC="p8";
+NET "green<0>" LOC="n8";
+NET "blue<1>" LOC="u4";
+NET "blue<0>" LOC="u5";

diff --git a/VTerm.v b/VTerm.v
new file mode 100644 (file)
index 0000000..62591bf
--- /dev/null
+++ b/VTerm.v
@@ -0,0 +1,90 @@
+module MulDivDCM(input xtal, output clk);
+       parameter div = 5;
+       parameter mul = 2;
+       
+       wire CLKFX_BUF;
+       wire GND_BIT = 0;
+       BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
+                               .O(clk));
+       DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), 
+                       .CLKIN(xtal), 
+                       .DSSEN(GND_BIT), 
+                       .PSCLK(GND_BIT), 
+                       .PSEN(GND_BIT), 
+                       .PSINCDEC(GND_BIT), 
+                       .RST(GND_BIT), 
+                       .CLKFX(CLKFX_BUF));
+       defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
+       defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
+       defparam DCM_SP_INST.CLKFX_DIVIDE = div;
+       defparam DCM_SP_INST.CLKFX_MULTIPLY = mul;
+       defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+       defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
+       defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
+       defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+       defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
+       defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
+       defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+       defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
+       defparam DCM_SP_INST.PHASE_SHIFT = 0;
+       defparam DCM_SP_INST.STARTUP_WAIT = "TRUE";
+endmodule
+
+module VTerm(
+       input xtal,
+       output wire vs, hs,
+       output reg [2:0] red,
+       output reg [2:0] green,
+       output reg [1:0] blue
+       );
+       
+       wire clk25;
+
+       wire [11:0] x, y;
+       wire border;
+
+       MulDivDCM dcm25(xtal, clk25);
+       defparam dcm25.div = 4;
+       defparam dcm25.mul = 2;
+
+       SyncGen sync(clk25, vs, hs, x, y, border);
+       
+       always @(posedge clk25) begin
+               red <= border ? 0 : 3'b100;
+               green <= border ? 0 : 0;
+               blue <= border ? 0 : 0;
+       end
+endmodule
+
+module SyncGen(
+       input pixclk,
+       output reg vs, hs,
+       output reg [11:0] x, y,
+       output reg border);
+       
+       parameter XRES = 640;
+       parameter XFPORCH = 16;
+       parameter XSYNC = 96;
+       parameter XBPORCH = 48;
+       
+       parameter YRES = 480;
+       parameter YFPORCH = 10;
+       parameter YSYNC = 2;
+       parameter YBPORCH = 29;
+       
+       always @(posedge pixclk)
+       begin
+               if (x >= (XRES + XFPORCH + XSYNC + XBPORCH))
+               begin
+                       if (y >= (YRES + YFPORCH + YSYNC + YBPORCH))
+                               y = 0;
+                       else
+                               y = y + 1;
+                       x = 0;
+               end else
+                       x = x + 1;
+               hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC));
+               vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC));
+               border <= (x > XRES) || (y > YRES);
+       end
+endmodule

diff --git a/VTerm.xst b/VTerm.xst
new file mode 100644 (file)
index 0000000..d91f1a5
--- /dev/null
+++ b/VTerm.xst
@@ -0,0 +1,57 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn VTerm.prj
+-ifmt mixed
+-ofn VTerm
+-ofmt NGC
+-p xc3s500e-5-fg320
+-top VTerm
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso VTerm.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5

diff --git a/impact.cmd b/impact.cmd
new file mode 100644 (file)
index 0000000..752fa2b
--- /dev/null
+++ b/impact.cmd
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port svf -file "XXX.svf"
+addDevice -p 1 -file "XXX.bit"
+addDevice -p 2 -part xcf04s
+Program -p 1 -defaultVersion 0
+quit
+