whoops.

diff --git a/Makefile b/Makefile
index aab7d1759602ae6b86939a829ca5f729b81b7319..f6ef7b25e5219cf7b31137f1e8e36382f54f581f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -42,7 +42,7 @@ $(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf
        ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p $(CHIP) "$(TARGET).ngc" $(TARGET).ngd
 
 $(TARGET).vm6: $(TARGET).ngd
-       cpldfit -p $(CHIP) -power std $(TARGET).ngd -inputs 10 
+       cpldfit -p $(CHIP) -power std $(TARGET).ngd -inputs 12 -pterms 10 
 
 $(TARGET).jed: $(TARGET).vm6
        hprep6 -i $(TARGET).vm6

diff --git a/POSLink.ucf b/POSLink.ucf
index b9f3ece1f0f2be99a28ba8bce32f166028e3fab2..2a9cbd7ffa4ce2df517594df27895223dd39ea39 100644 (file)
--- a/POSLink.ucf
+++ b/POSLink.ucf
@@ -1,11 +1,11 @@
 NET "xtal" LOC="P43";
 NET "xtal" BUFG=CLK;
 
-NET "tos_inputs_e2<0>" LOC="P38";
-NET "tos_inputs_e2<1>" LOC="P39";
-NET "tos_inputs_e2<2>" LOC="P32";
-NET "tos_inputs_e2<3>" LOC="P31";
-NET "tos_output"       LOC="P30";
+NET "tos_inputs_e2<0>" LOC="P30";
+NET "tos_inputs_e2<1>" LOC="P31";
+NET "tos_inputs_e2<2>" LOC="P38";
+NET "tos_inputs_e2<3>" LOC="P39";
+NET "tos_output"       LOC="P32";
 NET "data_output"      LOC="P3";
 NET "serial_e2"        LOC="P2";
 NET "anode<0>"         LOC="P29";

diff --git a/POSLink.v b/POSLink.v
index ce96bd0d4125ff5e6c99f88fff3299e6cbccb66e..6428436dd4ae0e600566a4a405b199933766ab98 100644 (file)
--- a/POSLink.v
+++ b/POSLink.v
@@ -5,8 +5,8 @@ module POSLink(
        input [1:0] buttons,
        output tos_output,
        output reg data_output,
-       output reg [3:0] anode,
-       output reg [7:0] cathode);
+       output reg [3:0] anode = 4'hF,
+       output reg [7:0] cathode = 8'hFF);
        
        reg [3:0] tos_inputs_e;
        reg [3:0] tos_inputs;
@@ -49,7 +49,8 @@ wire [4:0] edge_counter;
                tos_select = data[11:10];
        end
 
-       wire [7:0] output_stuff = { 2'b0, buttons, tos_good };
+       // Buttons are active-low, so invert them. 
+       wire [7:0] output_stuff = { 2'b0, ~buttons, tos_good };
 
        always @(*)
                data_output = output_stuff[current_bit[2:0]];
@@ -117,7 +118,7 @@ module TOS_Detect(
                tos_input_1a <= tos_input;
        wire transition = tos_input ^ tos_input_1a;
        
-       reg [3:0] lasttx = 0;
+       reg [4:0] lasttx = 0;
        always @(posedge xtal) begin
                if (transition) begin
                        if (lasttx < 2) /* Too soon! */