]> Joshua Wise's Git repositories - poslink.git/commitdiff
initial commit
authorJoshua Wise <jwise@andrew.cmu.edu>
Sat, 19 Feb 2011 07:26:36 +0000 (02:26 -0500)
committerJoshua Wise <jwise@andrew.cmu.edu>
Sat, 19 Feb 2011 07:26:36 +0000 (02:26 -0500)
Makefile [new file with mode: 0644]
POSLink.ucf [new file with mode: 0644]
POSLink.v [new file with mode: 0644]
POSLink.xst [new file with mode: 0644]
impact.cmd [new file with mode: 0644]

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..84031f7
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,76 @@
+TARGET = POSLink
+VLOGS = POSLink.v
+VLOGS_ALL = $(VLOGS)
+
+all: fpga_target
+
+scancodes.unshifted.hex: scancodes.txt
+       cut -f3 -d, scancodes.txt > scancodes.unshifted.hex
+
+scancodes.shifted.hex: scancodes.txt
+       cut -f4 -d, scancodes.txt > scancodes.shifted.hex
+
+BITGEN_OPTS = \
+       -w \
+       -g DebugBitstream:No \
+       -g Binary:no \
+       -g CRC:Enable \
+       -g ConfigRate:1 \
+       -g ProgPin:PullUp \
+       -g DonePin:PullUp \
+       -g TckPin:PullUp \
+       -g TdiPin:PullUp \
+       -g TdoPin:PullUp \
+       -g TmsPin:PullUp \
+       -g UnusedPin:PullDown \
+       -g UserID:0xFFFFFFFF \
+       -g DCMShutdown:Disable \
+       -g StartUpClk:CClk \
+       -g DONE_cycle:4 \
+       -g GTS_cycle:5 \
+       -g GWE_cycle:6 \
+       -g LCK_cycle:NoWait \
+       -g Security:None \
+       -g DonePipe:No \
+       -g DriveDone:No
+
+fpga_target: $(TARGET).svf
+
+$(TARGET).ngc: $(TARGET).xst $(VLOGS_ALL)
+       @mkdir -p xst/projnav.tmp
+       @echo work > $(TARGET).lso
+       @rm -f $(TARGET).prj
+       @for i in $(VLOGS); do echo verilog work '"'$$i'"' >> $(TARGET).prj; done
+       xst -ifn $(TARGET).xst -ofn $(TARGET).syr
+
+$(TARGET).ngd: $(TARGET).ngc $(TARGET).ucf
+       ngdbuild -dd _ngo -uc $(TARGET).ucf -nt timestamp -p xc3s1200e-fg320-5 "$(TARGET).ngc" $(TARGET).ngd
+
+$(TARGET)_map.ncd: $(TARGET).ngd
+       map -p xc3s1200e-fg320-5 -cm area -pr off -k 4 -c 100 -o $(TARGET)_map.ncd $(TARGET).ngd $(TARGET).pcf
+
+$(TARGET).ncd: $(TARGET)_map.ncd
+       par -w -ol std -t 1 $(TARGET)_map.ncd $(TARGET).ncd $(TARGET).pcf
+
+$(TARGET).twr: $(TARGET)_map.ncd
+       trce -e 3 -s 5 -xml $(TARGET) $(TARGET).ncd -o $(TARGET).twr $(TARGET).pcf -ucf $(TARGET).ucf
+
+$(TARGET).bit: $(TARGET).ncd
+       bitgen $(BITGEN_OPTS) $(TARGET).ncd
+
+$(TARGET).svf: $(TARGET).bit impact.cmd
+       sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
+       impact -batch tmp.cmd
+
+clean:
+       rm -f $(TARGET).bgn $(TARGET).ngc $(TARGET).svf $(TARGET).ngd $(TARGET).bit $(TARGET).twr $(TARGET).ncd $(TARGET)_map.ncd $(TARGET)_map.*
+       rm -f $(TARGET).bld $(TARGET).drc $(TARGET)_ngdbuild.xrpt $(TARGET)_pad.* $(TARGET).pad $(TARGET).par $(TARGET)_par.xrpt $(TARGET).ngr
+       rm -f $(TARGET).pcf $(TARGET)_summary.xml $(TARGET).unroutes $(TARGET)_usage.xml $(TARGET)_xst.xrpt $(TARGET).syr $(TARGET).ptwx $(TARGET).xpi
+       rm -rf xst
+       rm -rf xlnx_auto_*
+       rm -rf _ngo
+       rm -f tmp.cmd
+       rm -f _impactbatch.log
+       rm -f $(TARGET).prj
+       rm -f $(TARGET).lso
+
diff --git a/POSLink.ucf b/POSLink.ucf
new file mode 100644 (file)
index 0000000..456487b
--- /dev/null
@@ -0,0 +1,14 @@
+NET "xtal" LOC="b8";
+
+NET "tos_inputs_e2<0>" LOC="H16";
+NET "tos_inputs_e2<1>" LOC="G13";
+NET "tos_inputs_e2<2>" LOC="J16";
+NET "tos_output"       LOC="G15";
+NET "leds<0>"          LOC="J14";
+NET "leds<1>"          LOC="J15";
+NET "leds<2>"          LOC="K15";
+NET "leds<3>"          LOC="K14";
+NET "sw<0>"            LOC="G18";
+NET "sw<1>"            LOC="H18";
+NET "sw<2>"            LOC="K18";
+NET "sw<3>"            LOC="K17";
diff --git a/POSLink.v b/POSLink.v
new file mode 100644 (file)
index 0000000..3dc9576
--- /dev/null
+++ b/POSLink.v
@@ -0,0 +1,72 @@
+module POSLink(
+       input xtal,
+       input [2:0] tos_inputs_e2,
+       input [3:0] sw,
+       output reg [3:0] leds,
+       output reg tos_output);
+       
+       reg [2:0] tos_inputs_e;
+       reg [2:0] tos_inputs;
+       wire [2:0] tos_good;
+       
+       always @(posedge xtal) begin
+               tos_inputs_e <= tos_inputs_e2;
+               tos_inputs <= tos_inputs_e;
+       end
+       
+       /* 100ns -> 1000ns */
+       
+       always @(*) begin
+               leds[3:0] = 4'h0;
+               
+               if (sw[2] || (tos_good[2] && ~sw[1] && ~sw[0])) begin
+                       tos_output = tos_inputs[2];
+                       leds[2] = 1;
+               end else if (sw[1] | (tos_good[1] && ~sw[0])) begin
+                       tos_output = tos_inputs[1];
+                       leds[1] = 1;
+               end else if (sw[0] | tos_good[0]) begin
+                       tos_output = tos_inputs[0];
+                       leds[0] = 1;
+               end else
+                       tos_output = sw[3];
+               leds[3] = tos_output;
+       end
+       
+       TOS_Detect detect[2:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good));
+endmodule
+
+/* xtal: 50MHz (==20ns)
+ * Minimum: 100ns (we'll allow 60ns for good measure)
+ *          5 cycles (we'll allow 3 for good measure)
+ * Maximum: 1000ns (we'll allow 1200ns for good measure)
+ *          50 cycles (we'll allow 60 for good measure)
+ */
+module TOS_Detect(
+       input xtal,
+       input tos_input,
+       output reg tos_good = 0);
+       
+       reg tos_input_1a = 0;
+       always @(posedge xtal)
+               tos_input_1a <= tos_input;
+       wire transition = tos_input ^ tos_input_1a;
+       
+       reg [5:0] lasttx = 0;
+       always @(posedge xtal) begin
+               if (transition) begin
+                       if (lasttx < 3) /* Too soon! */
+                               tos_good <= 0;
+                       else if (lasttx > 60) /* Too late! */
+                               tos_good <= 0;
+                       else /* OK by me. */
+                               tos_good <= 1;
+                       lasttx <= 0;
+               end else begin
+                       if (lasttx != 63)
+                               lasttx <= lasttx + 1;
+                       else
+                               tos_good <= 0;
+               end
+       end
+endmodule
diff --git a/POSLink.xst b/POSLink.xst
new file mode 100644 (file)
index 0000000..67af972
--- /dev/null
@@ -0,0 +1,57 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn POSLink.prj
+-ifmt mixed
+-ofn POSLink
+-ofmt NGC
+-p xc3s500e-5-fg320
+-top POSLink
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso POSLink.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/impact.cmd b/impact.cmd
new file mode 100644 (file)
index 0000000..752fa2b
--- /dev/null
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port svf -file "XXX.svf"
+addDevice -p 1 -file "XXX.bit"
+addDevice -p 2 -part xcf04s
+Program -p 1 -defaultVersion 0
+quit
+
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