3 input [2:0] tos_inputs_e2,
6 output reg tos_output);
8 reg [2:0] tos_inputs_e;
12 always @(posedge xtal) begin
13 tos_inputs_e <= tos_inputs_e2;
14 tos_inputs <= tos_inputs_e;
22 if (sw[2] || (tos_good[2] && ~sw[1] && ~sw[0])) begin
23 tos_output = tos_inputs[2];
25 end else if (sw[1] | (tos_good[1] && ~sw[0])) begin
26 tos_output = tos_inputs[1];
28 end else if (sw[0] | tos_good[0]) begin
29 tos_output = tos_inputs[0];
36 TOS_Detect detect[2:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good));
39 /* xtal: 50MHz (==20ns)
40 * Minimum: 100ns (we'll allow 60ns for good measure)
41 * 5 cycles (we'll allow 3 for good measure)
42 * Maximum: 1000ns (we'll allow 1200ns for good measure)
43 * 50 cycles (we'll allow 60 for good measure)
48 output reg tos_good = 0);
51 always @(posedge xtal)
52 tos_input_1a <= tos_input;
53 wire transition = tos_input ^ tos_input_1a;
56 always @(posedge xtal) begin
58 if (lasttx < 3) /* Too soon! */
60 else if (lasttx > 60) /* Too late! */