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1 | module POSLink( | |
2 | input xtal, | |
3 | input [2:0] tos_inputs_e2, | |
4 | input [3:0] sw, | |
5 | output reg [3:0] leds, | |
6 | output reg tos_output); | |
7 | ||
8 | reg [2:0] tos_inputs_e; | |
9 | reg [2:0] tos_inputs; | |
10 | wire [2:0] tos_good; | |
11 | ||
12 | always @(posedge xtal) begin | |
13 | tos_inputs_e <= tos_inputs_e2; | |
14 | tos_inputs <= tos_inputs_e; | |
15 | end | |
16 | ||
17 | /* 100ns -> 1000ns */ | |
18 | ||
19 | always @(*) begin | |
20 | leds[3:0] = 4'h0; | |
21 | ||
22 | if (sw[2] || (tos_good[2] && ~sw[1] && ~sw[0])) begin | |
23 | tos_output = tos_inputs[2]; | |
24 | leds[2] = 1; | |
25 | end else if (sw[1] | (tos_good[1] && ~sw[0])) begin | |
26 | tos_output = tos_inputs[1]; | |
27 | leds[1] = 1; | |
28 | end else if (sw[0] | tos_good[0]) begin | |
29 | tos_output = tos_inputs[0]; | |
30 | leds[0] = 1; | |
31 | end else | |
32 | tos_output = sw[3]; | |
33 | leds[3] = tos_output; | |
34 | end | |
35 | ||
36 | TOS_Detect detect[2:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good)); | |
37 | endmodule | |
38 | ||
39 | /* xtal: 50MHz (==20ns) | |
40 | * Minimum: 100ns (we'll allow 60ns for good measure) | |
41 | * 5 cycles (we'll allow 3 for good measure) | |
42 | * Maximum: 1000ns (we'll allow 1200ns for good measure) | |
43 | * 50 cycles (we'll allow 60 for good measure) | |
44 | */ | |
45 | module TOS_Detect( | |
46 | input xtal, | |
47 | input tos_input, | |
48 | output reg tos_good = 0); | |
49 | ||
50 | reg tos_input_1a = 0; | |
51 | always @(posedge xtal) | |
52 | tos_input_1a <= tos_input; | |
53 | wire transition = tos_input ^ tos_input_1a; | |
54 | ||
55 | reg [5:0] lasttx = 0; | |
56 | always @(posedge xtal) begin | |
57 | if (transition) begin | |
58 | if (lasttx < 3) /* Too soon! */ | |
59 | tos_good <= 0; | |
60 | else if (lasttx > 60) /* Too late! */ | |
61 | tos_good <= 0; | |
62 | else /* OK by me. */ | |
63 | tos_good <= 1; | |
64 | lasttx <= 0; | |
65 | end else begin | |
66 | if (lasttx != 63) | |
67 | lasttx <= lasttx + 1; | |
68 | else | |
69 | tos_good <= 0; | |
70 | end | |
71 | end | |
72 | endmodule |