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93bedefa JW |
1 | module POSLink( |
2 | input xtal, | |
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3 | input [3:0] tos_inputs_e2, |
4 | input serial_e2, | |
5 | input [1:0] buttons, | |
6 | output tos_output, | |
7 | output reg data_output, | |
8 | output reg [3:0] anode, | |
9 | output reg [7:0] cathode); | |
93bedefa | 10 | |
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11 | reg [3:0] tos_inputs_e; |
12 | reg [3:0] tos_inputs; | |
13 | reg serial_e; | |
14 | reg serial; | |
15 | ||
16 | wire [3:0] tos_good; | |
17 | ||
18 | /* Synchronize inputs */ | |
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19 | always @(posedge xtal) begin |
20 | tos_inputs_e <= tos_inputs_e2; | |
21 | tos_inputs <= tos_inputs_e; | |
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22 | serial_e <= serial_e2; |
23 | serial <= serial_e; | |
93bedefa | 24 | end |
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25 | |
26 | wire [11:0] data; | |
27 | wire data_good; | |
28 | ||
29 | reg [1:0] seg; | |
30 | ||
31 | always @(*) | |
32 | case (seg) | |
33 | 2'b00: anode = 4'b0111; | |
34 | 2'b01: anode = 4'b1011; | |
35 | 2'b10: anode = 4'b1101; | |
36 | 2'b11: anode = 4'b1110; | |
37 | endcase | |
38 | ||
39 | reg [1:0] tos_select; | |
40 | ||
0170e492 | 41 | wire [4:0] edge_counter; |
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42 | wire [3:0] current_bit; |
43 | ||
44 | assign tos_output = tos_inputs_e2[tos_select]; | |
45 | ||
93bedefa | 46 | always @(*) begin |
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47 | cathode = data[7:0]; |
48 | seg = data[9:8]; | |
49 | tos_select = data[11:10]; | |
93bedefa | 50 | end |
0170e492 | 51 | |
bb68ed9f | 52 | wire [7:0] output_stuff = { 2'b0, buttons, tos_good }; |
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53 | |
54 | always @(*) | |
55 | data_output = output_stuff[current_bit[2:0]]; | |
56 | ||
57 | TOS_Detect detect[3:0](.xtal(xtal), .tos_input(tos_inputs), .tos_good(tos_good)); | |
0170e492 | 58 | POS_Serial serinput(.xtal(xtal), .serial(serial), .data_reg(data), .current_bit(current_bit), .data_good(data_good), .edge_counter(edge_counter)); |
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59 | endmodule |
60 | ||
61 | ||
62 | module POS_Serial( | |
63 | input xtal, | |
64 | input serial, | |
65 | output reg [11:0] data_reg = 0, | |
66 | output reg [3:0] current_bit = 0, | |
0170e492 | 67 | output reg [4:0] edge_counter = 0, |
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68 | output reg data_good = 0); |
69 | ||
70 | reg serial_1a; | |
71 | ||
72 | always @(posedge xtal) | |
0170e492 | 73 | serial_1a <= serial; |
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74 | |
75 | wire edge_detect = serial ^ serial_1a; | |
76 | ||
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77 | |
78 | always @(posedge xtal) begin | |
0170e492 | 79 | data_good <= 0; |
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80 | |
81 | if (edge_detect) begin | |
82 | if (edge_counter == 31) begin | |
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83 | current_bit <= 0; |
84 | // data_reg <= 0; | |
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85 | end else begin |
86 | // data_reg[11:1] = data_reg[10:0]; | |
87 | // data_reg[0] = (edge_counter > 20); | |
0170e492 | 88 | data_reg[current_bit] <= ((edge_counter > 20) ? 1'b1 : 1'b0); |
23b3490b | 89 | if (current_bit == 11) begin |
0170e492 | 90 | current_bit <= 0; |
23b3490b | 91 | end else |
0170e492 | 92 | current_bit <= current_bit + 1; |
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93 | end |
94 | ||
0170e492 | 95 | edge_counter <= 0; |
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96 | end else begin |
97 | if (edge_counter != 31) | |
0170e492 | 98 | edge_counter <= edge_counter + 1; |
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99 | end |
100 | end | |
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101 | endmodule |
102 | ||
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103 | |
104 | /* xtal: 25MHz (==40ns) | |
105 | * Minimum: 100ns | |
106 | * 2 cycles (80 ns) | |
107 | * Maximum: 1000ns | |
108 | * 25 cycles (we'll allow 30 = 1200ns for good measure) | |
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109 | */ |
110 | module TOS_Detect( | |
111 | input xtal, | |
112 | input tos_input, | |
113 | output reg tos_good = 0); | |
114 | ||
115 | reg tos_input_1a = 0; | |
116 | always @(posedge xtal) | |
117 | tos_input_1a <= tos_input; | |
118 | wire transition = tos_input ^ tos_input_1a; | |
119 | ||
23b3490b | 120 | reg [3:0] lasttx = 0; |
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121 | always @(posedge xtal) begin |
122 | if (transition) begin | |
23b3490b | 123 | if (lasttx < 2) /* Too soon! */ |
93bedefa | 124 | tos_good <= 0; |
23b3490b | 125 | else if (lasttx > 30) /* Too late! */ |
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126 | tos_good <= 0; |
127 | else /* OK by me. */ | |
128 | tos_good <= 1; | |
129 | lasttx <= 0; | |
130 | end else begin | |
23b3490b | 131 | if (lasttx != 31) |
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132 | lasttx <= lasttx + 1; |
133 | else | |
134 | tos_good <= 0; | |
135 | end | |
136 | end | |
137 | endmodule | |
23b3490b | 138 |