pci_dump();
}
+void gbl_rls_handler(smi_event_t ev)
+{
+ unsigned long ecx;
+
+ ecx = *(unsigned char*)0xAFFD4;
+ dologf("ECX was %08x", ecx);
+ *(unsigned long*)0xAFFD4 = 0x2BADD00D;
+}
+
void smi_entry(void)
{
char statstr[512];
extern void timer_handler(smi_event_t ev);
extern void kbc_handler(smi_event_t ev);
+extern void gbl_rls_handler(smi_event_t ev);
void __firstrun_start() {
unsigned char *bp;
smi_register_handler(SMI_EVENT_DEVTRAP_KBC, kbc_handler);
smi_enable_event(SMI_EVENT_DEVTRAP_KBC);
+
+ smi_register_handler(SMI_EVENT_GBL_RLS, gbl_rls_handler);
+ smi_enable_event(SMI_EVENT_GBL_RLS);
smi_enable();
if (sts & ICH2_SMI_STS_BIOS_STS)
{
- output("Unhandled: BIOS_STS");
+ if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
+ output("Unhandled: BIOS_STS");
+ else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
+ _handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
}
inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
ICH2_DEVTRAP_EN_KBC_TRP_EN);
return 0;
+ case SMI_EVENT_GBL_RLS:
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+ inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
+ ICH2_SMI_EN_BIOS_EN);
+ return 0;
default:
return -1;
}
inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
~ICH2_DEVTRAP_EN_KBC_TRP_EN);
return 0;
+ case SMI_EVENT_GBL_RLS:
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+ inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
+ ~ICH2_SMI_EN_BIOS_EN);
+ return 0;
default:
return -1;
}