sprintf(thestr, "15-412! %08x %08x", smi_status(), counter);
strblit(thestr, 0, 0);
- if (inl(0x834) & 0x20)
- dolog("Warning: unhandled APM access");
if (inl(0x834) & 0x1000)
{
if (inl(0x844) & 0x1000) /* devact_sts */
outl(0x844, 0x1000); /* ack it */
}
}
- if (inl(0x834) & 0x4000)
- dolog("Long periodic timer");
if (inl(0x840) & 0x1000)
{
pci_dump();
outl(0x840, 0x1100);
outl(0x840, 0x0100);
}
- if (inl(0x834) & ~(0x4160))
- dologf("Unknown: %08x", inl(0x834) & ~(0x140));
+ smi_poll();
outlog();
outl(0xCF8, pcisave);
outb(0x3D4, vgasave);
-
- outl(0x848, 0x1000);
- outl(0x834, /*0x40*/0xFFFF); // ack the periodic IRQ
- outb(0x830, (inb(0x830) | 0x2) & ~0x40);
- outb(0x830, inb(0x830) | 0x40);
-
}
#include <io.h>
#include <smi.h>
#include <pci.h>
+#include <reg-82801b.h>
#include "vga-overlay.h"
void __firstrun_start() {
pci_write16(0, 31, 4, 0xC0, 0);
/* Turn on the SMIs we want */
- outb(0x830, inb(0x830) | 0x40);
+ outb(0x830, inb(0x830) | ICH2_SMI_EN_SWSMI_TMR_EN);
+ outb(0x848, ICH2_DEVTRAP_EN_KBC_TRP_EN);
smi_enable();
}
#include <pci.h>
#include <io.h>
#include <stdint.h>
+#include <vga-overlay.h>
#include <reg-82801b.h>
uint16_t _get_PMBASE()
return inl(smi_sts);
}
+void smi_poll()
+{
+ unsigned long sts = smi_status();
+
+ if (sts & ICH2_SMI_STS_BIOS_STS)
+ {
+ dolog("Unhandled: BIOS_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
+ {
+ dolog("Unhandled: LEGACY_USB_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_SLP_SMI_STS)
+ {
+ dolog("Unhandled: SLP_SMI_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_APM_STS)
+ {
+ dolog("Unhandled: APM_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_SWSMI_TMR_STS) // Ack it, then request another.
+ {
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+ inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) & ~ICH2_SMI_EN_SWSMI_TMR_EN);
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+ inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) | ICH2_SMI_EN_SWSMI_TMR_EN);
+ }
+
+ if (sts & ICH2_SMI_STS_PM1_STS_REG)
+ {
+ /* XXX -- trawl through PMBASE+00h to see what happened */
+ }
+
+ if (sts & ICH2_SMI_STS_GPE0_STS)
+ {
+ /* XXX -- trawl through GPE0_STS to see what happened */
+ }
+
+ if (sts & ICH2_SMI_STS_MCSMI_STS)
+ {
+ dolog("Unhandled: MCSMI_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_DEVMON_STS)
+ {
+ /* XXX -- trawl through DEVx_TRAP_STS to see what happened */
+ /* XXX -- trawl through DEVTRAP_STS to see what happened */
+ }
+
+ if (sts & ICH2_SMI_STS_TCO_STS)
+ {
+ dolog("Unhandled: TCO_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_PERIODIC_STS)
+ {
+ dolog("Unhandled: PERIODIC_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
+ {
+ dolog("Unhandled: SERIRQ_SMI_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
+ }
+
+ if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
+ {
+ dolog("Unhandled: SMBUS_SMI_STS");
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
+ }
+
+ if (smi_status())
+ dolog("WARNING: failed to clear SMI_STS!");
+
+ outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
+ inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
+ ICH2_SMI_EN_EOS |
+ ICH2_SMI_EN_GBL_SMI_EN);
+}
#define ICH2_SMI_STS_LEGACY_USB_STS (1 << 3)
#define ICH2_SMI_STS_BIOS_STS (1 << 2)
+#define ICH2_PMBASE_MON_SMI 0x40
+#define ICH2_MON_SMI_DEV7_TRAP_STS (1 << 15)
+#define ICH2_MON_SMI_DEV6_TRAP_STS (1 << 14)
+#define ICH2_MON_SMI_DEV5_TRAP_STS (1 << 13)
+#define ICH2_MON_SMI_DEV4_TRAP_STS (1 << 12)
+#define ICH2_MON_SMI_DEV7_TRAP_EN (1 << 11)
+#define ICH2_MON_SMI_DEV6_TRAP_EN (1 << 10)
+#define ICH2_MON_SMI_DEV5_TRAP_EN (1 << 9)
+#define ICH2_MON_SMI_DEV4_TRAP_EN (1 << 8)
+
+#define ICH2_PMBASE_DEVACT_STS 0x44
+#define ICH2_DEVACT_STS_ADLIB_ACT_STS (1 << 13)
+#define ICH2_DEVACT_STS_KBC_ACT_STS (1 << 12)
+#define ICH2_DEVACT_STS_MIDI_ACT_STS (1 << 11)
+#define ICH2_DEVACT_STS_AUDIO_ACT_STS (1 << 10)
+#define ICH2_DEVACT_STS_PIRQDH_ACT_STS (1 << 9)
+#define ICH2_DEVACT_STS_PIRQCG_ACT_STS (1 << 8)
+#define ICH2_DEVACT_STS_PIRQBF_ACT_STS (1 << 7)
+#define ICH2_DEVACT_STS_PIRQAE_ACT_STS (1 << 6)
+#define ICH2_DEVACT_STS_LEG_ACT_STS (1 << 5)
+#define ICH2_DEVACT_STS_IDES1_ACT_STS (1 << 3)
+#define ICH2_DEVACT_STS_IDES0_ACT_STS (1 << 2)
+#define ICH2_DEVACT_STS_IDEP1_ACT_STS (1 << 1)
+#define ICH2_DEVACT_STS_IDEP0_ACT_STS (1 << 0)
+
+#define ICH2_PMBASE_DEVTRAP_EN 0x48
+#define ICH2_DEVTRAP_EN_ADLIB_TRP_EN (1 << 13)
+#define ICH2_DEVTRAP_EN_KBC_TRP_EN (1 << 12)
+#define ICH2_DEVTRAP_EN_MIDI_TRP_EN (1 << 11)
+#define ICH2_DEVTRAP_EN_AUDIO_TRP_EN (1 << 10)
+#define ICH2_DEVTRAP_EN_LEG_TRP_EN (1 << 5)
+#define ICH2_DEVTRAP_EN_IDES1_TRP_EN (1 << 3)
+#define ICH2_DEVTRAP_EN_IDES0_TRP_EN (1 << 2)
+#define ICH2_DEVTRAP_EN_IDEP1_TRP_EN (1 << 1)
+#define ICH2_DEVTRAP_EN_IDEP0_TRP_EN (1 << 0)
+
#define ICH2_IDE_BUS 0
#define ICH2_IDE_DEV 31
#define ICH2_IDE_FN 1