Add needed files for build; I r retard.

diff --git a/MandelTop.xst b/MandelTop.xst
new file mode 100644 (file)
index 0000000..dd7b865
--- /dev/null
+++ b/MandelTop.xst
@@ -0,0 +1,57 @@
+set -tmpdir "/home/joshua/projects/fpga/MandelFPGA/xst/projnav.tmp"
+set -xsthdpdir "/home/joshua/projects/fpga/MandelFPGA/xst"
+run
+-ifn MandelTop.prj
+-ifmt mixed
+-ofn MandelTop
+-ofmt NGC
+-p xc3s1200e-5-fg320
+-top MandelTop
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso MandelTop.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5

diff --git a/mandelDCM.v b/mandelDCM.v
new file mode 100644 (file)
index 0000000..9f628d2
--- /dev/null
+++ b/mandelDCM.v
@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____ 
+//  /   /\/   / 
+// /___/  \  /    Vendor: Xilinx 
+// \   \   \/     Version : 10.1
+//  \   \         Application : xaw2verilog
+//  /   /         Filename : mandelDCM.v
+// /___/   /\     Timestamp : 03/27/2008 18:06:47
+// \   \  /  \ 
+//  \___\/\___\ 
+//
+//Command: xaw2verilog -intstyle /home/joshua/projects/fpga/MandelFPGA/mandelDCM.xaw -st mandelDCM.v
+//Design Name: mandelDCM
+//Device: xc3s500e-5fg320
+//
+// Module mandelDCM
+// Generated by Xilinx Architecture Wizard
+// Written for synthesis tool: XST
+// Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI
+// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.76 ns
+`timescale 1ns / 1ps
+
+module mandelDCM(CLKIN_IN, 
+                 CLKFX_OUT, 
+                 LOCKED_OUT);
+
+    input CLKIN_IN;
+   output CLKFX_OUT;
+   output LOCKED_OUT;
+   
+   wire CLKFX_BUF;
+   wire GND_BIT;
+   
+   assign GND_BIT = 0;
+   BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), 
+                         .O(CLKFX_OUT));
+   DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), 
+                       .CLKIN(CLKIN_IN), 
+                       .DSSEN(GND_BIT), 
+                       .PSCLK(GND_BIT), 
+                       .PSEN(GND_BIT), 
+                       .PSINCDEC(GND_BIT), 
+                       .RST(GND_BIT), 
+                       .CLKDV(), 
+                       .CLKFX(CLKFX_BUF), 
+                       .CLKFX180(), 
+                       .CLK0(), 
+                       .CLK2X(), 
+                       .CLK2X180(), 
+                       .CLK90(), 
+                       .CLK180(), 
+                       .CLK270(), 
+                       .LOCKED(LOCKED_OUT), 
+                       .PSDONE(), 
+                       .STATUS());
+   defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
+   defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_SP_INST.CLKFX_DIVIDE = 2;
+   defparam DCM_SP_INST.CLKFX_MULTIPLY = 3;
+   defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
+   defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
+   defparam DCM_SP_INST.PHASE_SHIFT = 0;
+   defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
+endmodule

diff --git a/pixDCM.v b/pixDCM.v
new file mode 100644 (file)
index 0000000..bb8a3a2
--- /dev/null
+++ b/pixDCM.v
@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____ 
+//  /   /\/   / 
+// /___/  \  /    Vendor: Xilinx 
+// \   \   \/     Version : 10.1
+//  \   \         Application : xaw2verilog
+//  /   /         Filename : pixDCM.v
+// /___/   /\     Timestamp : 03/27/2008 18:06:47
+// \   \  /  \ 
+//  \___\/\___\ 
+//
+//Command: xaw2verilog -intstyle /home/joshua/projects/fpga/MandelFPGA/pixDCM.xaw -st pixDCM.v
+//Design Name: pixDCM
+//Device: xc3s500e-5fg320
+//
+// Module pixDCM
+// Generated by Xilinx Architecture Wizard
+// Written for synthesis tool: XST
+// Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI
+// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.03 ns
+`timescale 1ns / 1ps
+
+module pixDCM(CLKIN_IN, 
+              CLKFX_OUT, 
+              LOCKED_OUT);
+
+    input CLKIN_IN;
+   output CLKFX_OUT;
+   output LOCKED_OUT;
+   
+   wire CLKFX_BUF;
+   wire GND_BIT;
+   
+   assign GND_BIT = 0;
+   BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), 
+                         .O(CLKFX_OUT));
+   DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), 
+                       .CLKIN(CLKIN_IN), 
+                       .DSSEN(GND_BIT), 
+                       .PSCLK(GND_BIT), 
+                       .PSEN(GND_BIT), 
+                       .PSINCDEC(GND_BIT), 
+                       .RST(GND_BIT), 
+                       .CLKDV(), 
+                       .CLKFX(CLKFX_BUF), 
+                       .CLKFX180(), 
+                       .CLK0(), 
+                       .CLK2X(), 
+                       .CLK2X180(), 
+                       .CLK90(), 
+                       .CLK180(), 
+                       .CLK270(), 
+                       .LOCKED(LOCKED_OUT), 
+                       .PSDONE(), 
+                       .STATUS());
+   defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
+   defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_SP_INST.CLKFX_DIVIDE = 4;
+   defparam DCM_SP_INST.CLKFX_MULTIPLY = 2;
+   defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
+   defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
+   defparam DCM_SP_INST.PHASE_SHIFT = 0;
+   defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
+endmodule