new ctoreadmemb

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index 6762c0fe9839527088a5a460363b616d26f8d97e..b6fbae50dc02aa816c6fdf69b532160dd61f6197 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -69,19 +69,18 @@ module NaiveMultiplier(
        always @(posedge clk)
        begin
                {ovf,out} <=
        always @(posedge clk)
        begin
                {ovf,out} <=

-                       (((y[12] ? (x     ) : 0)  +
-                         (y[11] ? (x >> 1) : 0)  +
-                         (y[10] ? (x >> 2) : 0)) +
-                       (((y[9]  ? (x >> 3) : 0)  +
-                         (y[8]  ? (x >> 4) : 0))+
-                   ((y[7]  ? (x >> 5) : 0)  +
+                       (((y[12] ? (x     ) : 0)   +
+                         (y[11] ? (x >> 1) : 0)   +
+                         (y[10] ? (x >> 2) : 0))  +
+                       (((y[9]  ? (x >> 3) : 0)   +
+                         (y[8]  ? (x >> 4) : 0))  +
+                        ((y[7]  ? (x >> 5) : 0)   +

                          (y[6]  ? (x >> 6) : 0))))+
                          (y[6]  ? (x >> 6) : 0))))+

-                         
-                       (((y[5]  ? (x >> 7) : 0)  +
-                         (y[4]  ? (x >> 8) : 0)+
-                         (y[3]  ? (x >> 9) : 0)) +
-                        ((y[2]  ? (x >> 10): 0) +
-                         (y[1]  ? (x >> 11): 0)  +
+                       (((y[5]  ? (x >> 7) : 0)   +
+                         (y[4]  ? (x >> 8) : 0)   +
+                         (y[3]  ? (x >> 9) : 0))  +
+                        ((y[2]  ? (x >> 10): 0)   +
+                         (y[1]  ? (x >> 11): 0)   +

                          (y[0]  ? (x >> 12): 0)));
                sign <= xsign ^ ysign;
        end
                          (y[0]  ? (x >> 12): 0)));
                sign <= xsign ^ ysign;
        end


@@ -118,7 +117,7 @@ module MandelUnit(
        wire [14:0] ri, diff;
        wire [15:0] twocdiff;
        wire r2sign, i2sign, risign, dsign;
        wire [14:0] ri, diff;
        wire [15:0] twocdiff;
        wire r2sign, i2sign, risign, dsign;

-       wire [13:0] bigsum;
+       wire [14:0] bigsum;

        wire bigsum_ovf;
 
        reg [12:0] xd, yd;
        wire bigsum_ovf;
 
        reg [12:0] xd, yd;


@@ -132,8 +131,36 @@ module MandelUnit(
        Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
        Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
 
        Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
        Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
 

-       assign bigsum = r2[12:0] + i2[12:0];
-       assign bigsum_ovf = bigsum[13] | r2[13] | i2[13];
+       assign bigsum = r2[13:0] + i2[13:0];
+       wire shnasto = bigsum[14];
+       wire shnasto2 =         // o shi
+               ((r[12] & i[12]) |
+               ((r[12] ^ i[12]) &
+               ((r[11] & i[11]) |
+               ((r[11] ^ i[11]) &
+               ((r[10] & i[10]) |
+               ((r[10] ^ i[10]) &
+               ((r[ 9] & i[ 9]) |
+               ((r[ 9] ^ i[ 9]) &
+               ((r[ 8] & i[ 8]) |
+               ((r[ 8] ^ i[ 8]) &
+               ((r[ 7] & i[ 7]) |
+               ((r[ 7] ^ i[ 7]) &
+               ((r[ 6] & i[ 6]) |
+               ((r[ 6] ^ i[ 6]) &
+               ((r[ 5] & i[ 5]) |
+               ((r[ 5] ^ i[ 5]) &
+               ((r[ 4] & i[ 4]) |
+               ((r[ 4] ^ i[ 4]) &
+               ((r[ 3] & i[ 3]) |
+               ((r[ 3] ^ i[ 3]) &
+               ((r[ 2] & i[ 2]) |
+               ((r[ 2] ^ i[ 2]) &
+               ((r[ 1] & i[ 1]) |
+               ((r[ 1] ^ i[ 1]) &
+                (r[ 0] & i[ 0])
+               ))))))))))))))))))))))));
+       assign bigsum_ovf = shnasto | r2[13] | i2[13];

        
        assign twocdiff = r2 - i2;
        assign diff = twocdiff[15] ? -twocdiff : twocdiff;
        
        assign twocdiff = r2 - i2;
        assign diff = twocdiff[15] ? -twocdiff : twocdiff;


@@ -379,7 +406,7 @@ module MandelTop(
        input left, right, up, down, rst, cycle, logooff,
        input [2:0] scale);
 
        input left, right, up, down, rst, cycle, logooff,
        input [2:0] scale);
 

-       wire pixclk, mclk, gclk2, clk;
+       wire pixclk, mclk, clk;

        wire dcm1ok, dcm2ok;
        assign dcmok = dcm1ok && dcm2ok;
        
        wire dcm1ok, dcm2ok;
        assign dcmok = dcm1ok && dcm2ok;