bring in the make buildsystem for MandelFPGA

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index 6762c0fe9839527088a5a460363b616d26f8d97e..165a09555a4712c243d578a62a709b9127971f0b 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -5,6 +5,8 @@
  * An implementation of a pipelined algorithm to calculate the Mandelbrot set
  * in real time on an FPGA.
  */
+ 
+/* verilator lint_off WIDTH */
 
 `define XRES 640
 `define YRES 480
@@ -69,20 +71,19 @@ module NaiveMultiplier(
        always @(posedge clk)
        begin
                {ovf,out} <=
-                       (((y[12] ? (x     ) : 0)  +
-                         (y[11] ? (x >> 1) : 0)  +
-                         (y[10] ? (x >> 2) : 0)) +
-                       (((y[9]  ? (x >> 3) : 0)  +
-                         (y[8]  ? (x >> 4) : 0))+
-                   ((y[7]  ? (x >> 5) : 0)  +
-                         (y[6]  ? (x >> 6) : 0))))+
-                         
-                       (((y[5]  ? (x >> 7) : 0)  +
-                         (y[4]  ? (x >> 8) : 0)+
-                         (y[3]  ? (x >> 9) : 0)) +
-                        ((y[2]  ? (x >> 10): 0) +
-                         (y[1]  ? (x >> 11): 0)  +
-                         (y[0]  ? (x >> 12): 0)));
+                       (((y[12] ? (x       ) : 0)   +
+                         (y[11] ? (x[12:1]) : 0)   +
+                         (y[10] ? (x[12:2]) : 0))  +
+                       (((y[9]  ? (x[12:3]) : 0)   +
+                         (y[8]  ? (x[12:4]) : 0))  +
+                        ((y[7]  ? (x[12:5]) : 0)   +
+                         (y[6]  ? (x[12:6]) : 0))))+
+                       (((y[5]  ? (x[12:7]) : 0)   +
+                         (y[4]  ? (x[12:8]) : 0)   +
+                         (y[3]  ? (x[12:9]) : 0))  +
+                        ((y[2]  ? (x[12:10]): 0)   +
+                         (y[1]  ? (x[12:11]): 0)   +
+                         (y[0]  ? (x[12]): 0)));
                sign <= xsign ^ ysign;
        end
 
@@ -118,7 +119,7 @@ module MandelUnit(
        wire [14:0] ri, diff;
        wire [15:0] twocdiff;
        wire r2sign, i2sign, risign, dsign;
-       wire [13:0] bigsum;
+       wire [14:0] bigsum;
        wire bigsum_ovf;
 
        reg [12:0] xd, yd;
@@ -132,8 +133,8 @@ module MandelUnit(
        Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
        Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);
 
-       assign bigsum = r2[12:0] + i2[12:0];
-       assign bigsum_ovf = bigsum[13] | r2[13] | i2[13];
+       assign bigsum = r2[13:0] + i2[13:0];
+       assign bigsum_ovf = bigsum[14];
        
        assign twocdiff = r2 - i2;
        assign diff = twocdiff[15] ? -twocdiff : twocdiff;
@@ -210,8 +211,8 @@ module Mandelbrot(
        wire [13:0] nx, ny;
        wire rxsign, rysign;
        
-       assign nx = x + xofs;
-       assign ny = y + yofs;
+       assign nx = {2'b0,x} + {2'b0,xofs};
+       assign ny = {2'b0,y} + {2'b0,yofs};
        assign rx = (nx[13] ? -nx[12:0] : nx[12:0]) << scale;
        assign rxsign = nx[13];
        assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
@@ -224,12 +225,14 @@ module Mandelbrot(
        wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
        wire [7:0] curiter[`MAXOUTN:0];
        
-       reg [14:0] initx, inity, initr, initi;
+       reg [12:0] initx, inity;
+       reg [14:0] initr, initi;
        reg [7:0] initci, initb;
        reg initxs, initys, initrs, initis;
        
        // Values after the number of iterations denoted by the subscript.
-       reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
+       reg [12:0] stagex [2:1], stagey [2:1];
+       reg [14:0] stager [2:1], stagei [2:1];
        reg [7:0] stageci [2:1], stageb [2:1];
        reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];
        
@@ -245,10 +248,10 @@ module Mandelbrot(
                inity <= (state[2]) ? ry :
                       (state[0]) ? stagey[1] :
                       (state[1]) ? stagey[2] : 0;
-               initr <= (state[2]) ? rx :
+               initr <= (state[2]) ? {2'b0,rx} :
                       (state[0]) ? stager[1] :
                       (state[1]) ? stager[2] : 0;
-               initi <= (state[2]) ? ry :
+               initi <= (state[2]) ? {2'b0,ry} :
                       (state[0]) ? stagei[1] :
                       (state[1]) ? stagei[2] : 0;
                initxs <= (state[2]) ? rxsign :
@@ -289,6 +292,7 @@ module Mandelbrot(
                        3'b001: state <= 3'b010;
                        3'b010: state <= 3'b100;
                        3'b100: state <= 3'b001;
+                       default: begin $display("invalid state"); $finish; end
                        endcase
        
                // Data output handling
@@ -373,13 +377,19 @@ module Logo(
 endmodule
 
 module MandelTop(
+`ifdef verilator
+       input pixclk, mclk,
+`else
        input gclk, output wire dcmok,
+`endif
        output wire vs, hs,
        output wire [2:0] red, green, output [1:0] blue,
        input left, right, up, down, rst, cycle, logooff,
        input [2:0] scale);
-
-       wire pixclk, mclk, gclk2, clk;
+       
+`ifdef verilator
+`else
+       wire pixclk, mclk, clk;
        wire dcm1ok, dcm2ok;
        assign dcmok = dcm1ok && dcm2ok;
        
@@ -396,7 +406,8 @@ module MandelTop(
                .CLKFX_OUT(mclk),
                .LOCKED_OUT(dcm2ok)
                );
-       
+`endif
+
        wire border;
        wire [11:0] x, y;
        reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;
@@ -409,7 +420,7 @@ module MandelTop(
        wire [1:0] mandelb, logob;
        
        SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
-       Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
+       Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 8'b0, scale, mandelr, mandelg, mandelb);
        Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
        
        assign {red,green,blue} =