always @(posedge clk)
begin
{ovf,out} <=
- (((y[12] ? (x ) : 0) +
- (y[11] ? (x >> 1) : 0) +
- (y[10] ? (x >> 2) : 0)) +
- (((y[9] ? (x >> 3) : 0) +
- (y[8] ? (x >> 4) : 0))+
- ((y[7] ? (x >> 5) : 0) +
+ (((y[12] ? (x ) : 0) +
+ (y[11] ? (x >> 1) : 0) +
+ (y[10] ? (x >> 2) : 0)) +
+ (((y[9] ? (x >> 3) : 0) +
+ (y[8] ? (x >> 4) : 0)) +
+ ((y[7] ? (x >> 5) : 0) +
(y[6] ? (x >> 6) : 0))))+
-
- (((y[5] ? (x >> 7) : 0) +
- (y[4] ? (x >> 8) : 0)+
- (y[3] ? (x >> 9) : 0)) +
- ((y[2] ? (x >> 10): 0) +
- (y[1] ? (x >> 11): 0) +
+ (((y[5] ? (x >> 7) : 0) +
+ (y[4] ? (x >> 8) : 0) +
+ (y[3] ? (x >> 9) : 0)) +
+ ((y[2] ? (x >> 10): 0) +
+ (y[1] ? (x >> 11): 0) +
(y[0] ? (x >> 12): 0)));
sign <= xsign ^ ysign;
end
input left, right, up, down, rst, cycle, logooff,
input [2:0] scale);
- wire pixclk, mclk, gclk2, clk;
+ wire pixclk, mclk, clk;
wire dcm1ok, dcm2ok;
assign dcmok = dcm1ok && dcm2ok;