Clean up and turn the iout and rout into twos comp. I think this made our slice...

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index 61cb8f1d9991a72ae15261f8b2bd8781e6840108..ccc11c799aa8497972563274db3949f9cc220d5c 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -64,22 +64,23 @@ module NaiveMultiplier(
        input xsign, ysign,
        output reg [12:0] out,
        output reg sign,
        input xsign, ysign,
        output reg [12:0] out,
        output reg sign,

-       output reg [1:0] ovf);
+       output reg ovf);

 
        always @(posedge clk)
        begin
                {ovf,out} <=
                        (((y[12] ? (x     ) : 0)  +
                          (y[11] ? (x >> 1) : 0)  +
 
        always @(posedge clk)
        begin
                {ovf,out} <=
                        (((y[12] ? (x     ) : 0)  +
                          (y[11] ? (x >> 1) : 0)  +

-                         (y[10] ? (x >> 2) : 0)  +
-                         (y[9]  ? (x >> 3) : 0)) +
-                        ((y[8]  ? (x >> 4) : 0)  +
-                         (y[7]  ? (x >> 5) : 0)  +
-                         (y[6]  ? (x >> 6) : 0)))+
+                         (y[10] ? (x >> 2) : 0)) +
+                       (((y[9]  ? (x >> 3) : 0)  +
+                         (y[8]  ? (x >> 4) : 0))+
+                   ((y[7]  ? (x >> 5) : 0)  +
+                         (y[6]  ? (x >> 6) : 0))))+
+                         

                        (((y[5]  ? (x >> 7) : 0)  +
                        (((y[5]  ? (x >> 7) : 0)  +

-                         (y[4]  ? (x >> 8) : 0)  +
+                         (y[4]  ? (x >> 8) : 0)+

                          (y[3]  ? (x >> 9) : 0)) +
                          (y[3]  ? (x >> 9) : 0)) +

-                        ((y[2]  ? (x >> 10): 0)  +
+                        ((y[2]  ? (x >> 10): 0) +

                          (y[1]  ? (x >> 11): 0)  +
                          (y[0]  ? (x >> 12): 0)));
                sign <= xsign ^ ysign;
                          (y[1]  ? (x >> 11): 0)  +
                          (y[0]  ? (x >> 12): 0)));
                sign <= xsign ^ ysign;


@@ -93,12 +94,13 @@ module Multiplier(
        input xsign, ysign,
        output wire [12:0] out,
        output wire sign,
        input xsign, ysign,
        output wire [12:0] out,
        output wire sign,

-       output wire [1:0] overflow);
+       output wire overflow);

 
        NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
 
 endmodule
 
 
        NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
 
 endmodule
 

+// Yuq.

 module MandelUnit(
        input clk,
        input [12:0] x, y,
 module MandelUnit(
        input clk,
        input [12:0] x, y,


@@ -115,27 +117,29 @@ module MandelUnit(
        wire [14:0] r2, i2, ri, diff;
        wire [15:0] twocdiff;
        wire r2sign, i2sign, risign, dsign;
        wire [14:0] r2, i2, ri, diff;
        wire [15:0] twocdiff;
        wire r2sign, i2sign, risign, dsign;

-       wire [16:0] bigsum;
+       wire [15:0] bigsum;

        wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
 
        reg [12:0] xd, yd;
        wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
 
        reg [12:0] xd, yd;

-       reg rd, id;
+       reg ineedbaild;

        reg xsd, ysd;
        reg [7:0] ibaild, curiterd;
 
        assign ri[0] = 0;
 
        reg xsd, ysd;
        reg [7:0] ibaild, curiterd;
 
        assign ri[0] = 0;
 

-       Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[14:13]);
-       Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[14:13]);
-       Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, {throwaway,ri[14]});
+       Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
+       Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
+       Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);

 
        assign bigsum = r2 + i2;
 
        assign bigsum = r2 + i2;

-       assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
-       assign rin_ovf = rd;
-       assign iin_ovf = id;
+       assign bigsum_ovf = bigsum[15] | bigsum[14];
+       

        assign twocdiff = r2 - i2;
        assign diff = twocdiff[15] ? -twocdiff : twocdiff;
        assign dsign = twocdiff[15];
        assign twocdiff = r2 - i2;
        assign diff = twocdiff[15] ? -twocdiff : twocdiff;
        assign dsign = twocdiff[15];

+       
+       wire [15:0] twocrout = xd - diff;
+       wire [15:0] twociout = yd - ri;

 
        always @ (posedge clk)
        begin
 
        always @ (posedge clk)
        begin


@@ -149,28 +153,29 @@ module MandelUnit(
                ysout <= ysd;
                ibaild <= ibail;
                curiterd <= icuriter;
                ysout <= ysd;
                ibaild <= ibail;
                curiterd <= icuriter;

-               rd <= r[13] | r[14];
-               id <= i[13] | i[14];
+               ineedbaild <= r[13] | r[14] | i[13] | i[14];

 
 

+               // r^2 - i^2 + x

                if (xsd ^ dsign) begin
                if (xsd ^ dsign) begin

-                       if (diff > xd) begin
-                               rout <= diff - xd;
+                       if (twocrout[15]) begin // diff > xd
+                               rout <= -twocrout;

                                rsout <= dsign;
                        end else begin
                                rsout <= dsign;
                        end else begin

-                               rout <= xd - diff;
+                               rout <= twocrout;

                                rsout <= xsd;
                        end
                end else begin
                        rout <= diff + xd;
                                rsout <= xsd;
                        end
                end else begin
                        rout <= diff + xd;

-                       rsout <= xsd;
+                       rsout <= xsd;   // xsd == dsign

                end
                
                end
                

+               // 2 * r * i + y

                if (ysd ^ risign) begin
                if (ysd ^ risign) begin

-                       if (ri > yd) begin
-                               iout <= ri - yd;
+                       if (twociout[15]) begin // ri > yd
+                               iout <= -twociout;

                                isout <= risign;
                        end else begin
                                isout <= risign;
                        end else begin

-                               iout <= yd - ri;
+                               iout <= twociout;

                                isout <= ysd;
                        end
                end else begin
                                isout <= ysd;
                        end
                end else begin


@@ -180,7 +185,7 @@ module MandelUnit(
                
                // If we haven't bailed out, and we meet any of the bailout conditions,
                // bail out now.  Otherwise, leave the bailout at whatever it was before.
                
                // If we haven't bailed out, and we meet any of the bailout conditions,
                // bail out now.  Otherwise, leave the bailout at whatever it was before.

-               if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
+               if ((ibaild == 255) && (bigsum_ovf | ineedbaild))

                        obail <= curiterd;
                else
                        obail <= ibaild;
                        obail <= curiterd;
                else
                        obail <= ibaild;


@@ -210,7 +215,6 @@ module Mandelbrot(
        assign rxsign = nx[13];
        assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
        assign rysign = ny[13];
        assign rxsign = nx[13];
        assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
        assign rysign = ny[13];

-       

 
        wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
        wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
 
        wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
        wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];


@@ -219,9 +223,9 @@ module Mandelbrot(
        wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
        wire [7:0] curiter[`MAXOUTN:0];
        
        wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
        wire [7:0] curiter[`MAXOUTN:0];
        

-       wire [14:0] initx, inity, initr, initi;
-       wire [7:0] initci, initb;
-       wire initxs, initys, initrs, initis;
+       reg [14:0] initx, inity, initr, initi;
+       reg [7:0] initci, initb;
+       reg initxs, initys, initrs, initis;

        
        // Values after the number of iterations denoted by the subscript.
        reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
        
        // Values after the number of iterations denoted by the subscript.
        reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];


@@ -230,67 +234,71 @@ module Mandelbrot(
        
        reg [2:0] state = 3'b001;       // One-hot encoded state.
        
        
        reg [2:0] state = 3'b001;       // One-hot encoded state.
        

-       // On pixclk = 1,
-       //    A new value to be loaded comes in, and a value in need of loopback comes out.
-       // On pixclk = 0,
-       //    A new value in need of loopback comes in, and a completed value comes out.
-       
-       assign initx = state[0] ? rx :
-                      state[1] ? stagex[1] :
-                      stagex[2];
-       assign inity = state[0] ? ry :
-                      state[1] ? stagey[1] :
-                      stagey[2];
-       assign initr = state[0] ? rx :
-                      state[1] ? stager[1] :
-                      stager[2];
-       assign initi = state[0] ? ry :
-                      state[1] ? stagei[1] :
-                      stagei[2];
-       assign initxs = state[0] ? rxsign :
-                       state[1] ? stagexs[1] :
-                       stagexs[2];
-       assign initys = state[0] ? rysign :
-                       state[1] ? stageys[1] :
-                       stageys[2];
-       assign initrs = state[0] ? rxsign :
-                       state[1] ? stagers[1] :
-                       stagers[2];
-       assign initis = state[0] ? rysign :
-                       state[1] ? stageis[1] :
-                       stageis[2];
-       assign initb = state[0] ? 8'b11111111 :
-                      state[1] ? stageb[1] :
-                      stageb[2];
-       assign initci = state[0] ? 8'b00000000 :
-                       state[1] ? stageb[1] : 
-                       stageb[2];
+       // States are advanced one from what they should be, so that they'll
+       // get there on the _next_ mclk.
+       always @(posedge mclk)
+       begin
+               initx <= (state[2]) ? rx :
+                   (state[0]) ? stagex[1] :
+                   (state[1]) ? stagex[2] : 0;
+               inity <= (state[2]) ? ry :
+                      (state[0]) ? stagey[1] :
+                      (state[1]) ? stagey[2] : 0;
+               initr <= (state[2]) ? rx :
+                      (state[0]) ? stager[1] :
+                      (state[1]) ? stager[2] : 0;
+               initi <= (state[2]) ? ry :
+                      (state[0]) ? stagei[1] :
+                      (state[1]) ? stagei[2] : 0;
+               initxs <= (state[2]) ? rxsign :
+                       (state[0]) ? stagexs[1] :
+                       (state[1]) ? stagexs[2] : 0;
+               initys <= (state[2]) ? rysign :
+                       (state[0]) ? stageys[1] :
+                       (state[1]) ? stageys[2] : 0;
+               initrs <= (state[2]) ? rxsign :
+                       (state[0]) ? stagers[1] :
+                       (state[1]) ? stagers[2] : 0;
+               initis <= (state[2]) ? rysign :
+                       (state[0]) ? stageis[1] :
+                       (state[1]) ? stageis[2] : 0;
+               initb <= (state[2]) ? 8'b11111111 :
+                      (state[0]) ? stageb[1] :
+                      (state[1]) ? stageb[2] : 0;
+               initci <= (state[2]) ? 8'b00000000 :
+                       (state[0]) ? stageci[1] : 
+                       (state[1]) ? stageci[2] : 0;
+       end

        
        reg [7:0] out;
        
        reg [7:0] out;

-       reg typethea = 0;       // Whether we have typed the A.
-       reg statekick = 0;      // State needs to be kicked back to 3'b010 on the next mclk.
-
-       // This is guaranteed to converge after two pixclks.
-       //always @(negedge mclk)
-       //      if (pixclk && !typethea) begin
-       //              typethea <= 1;
-       //              statekick <= 1;
-       //      end else if (typethea) begin // This is the edge of the falling anus.
-       //              typethea <= 0;
-       //              statekick <= 0;
-       //      end
+       
+       // We detect when the state should be poked by a high negedge followed
+       // by a high posedge -- if that happens, then we're guaranteed that the
+       // state following the current state will be 3'b100.
+       reg lastneg;
+       always @(negedge mclk)
+               lastneg <= pixclk;

        
        always @(posedge mclk)
        begin
        
        always @(posedge mclk)
        begin

+               if (lastneg && pixclk)  // If a pixclk has happened, the state should be reset.
+                       state <= 3'b100;
+               else                                            // Otherwise, just poke it forward.
+                       case(state)
+                       3'b001: state <= 3'b010;
+                       3'b010: state <= 3'b100;
+                       3'b100: state <= 3'b001;
+                       endcase
+       

                // Data output handling
                if (state[0]) begin
                        {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
                end
                // Data output handling
                if (state[0]) begin
                        {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
                end

-               if (state[2]) begin
+               if (state[1]) begin

                        out <= ~mb[`MAXOUTN] + colorofs;
                end
                
                        out <= ~mb[`MAXOUTN] + colorofs;
                end
                

-               if (state[1]) begin             // PnR0 in, PnR2 out
+               if (state[0]) begin             // PnR0 in, PnR2 out

                        stagex[2] <= xprop[`MAXOUTN];
                        stagey[2] <= yprop[`MAXOUTN];
                        stager[2] <= mr[`MAXOUTN];
                        stagex[2] <= xprop[`MAXOUTN];
                        stagey[2] <= yprop[`MAXOUTN];
                        stager[2] <= mr[`MAXOUTN];


@@ -303,7 +311,7 @@ module Mandelbrot(
                        stageci[2] <= curiter[`MAXOUTN];
                end
                
                        stageci[2] <= curiter[`MAXOUTN];
                end
                

-               if (state[0]) begin     // PnR2 in, PnR1 out
+               if (state[2]) begin     // PnR2 in, PnR1 out

                        stagex[1] <= xprop[`MAXOUTN];
                        stagey[1] <= yprop[`MAXOUTN];
                        stager[1] <= mr[`MAXOUTN];
                        stagex[1] <= xprop[`MAXOUTN];
                        stagey[1] <= yprop[`MAXOUTN];
                        stager[1] <= mr[`MAXOUTN];


@@ -315,11 +323,6 @@ module Mandelbrot(
                        stageb[1] <= mb[`MAXOUTN];
                        stageci[1] <= curiter[`MAXOUTN];
                end
                        stageb[1] <= mb[`MAXOUTN];
                        stageci[1] <= curiter[`MAXOUTN];
                end

-               
-               if (statekick)          // If a pixclk has happened, the state should be reset.
-                       state <= 3'b010;
-               else                                            // Otherwise, just poke it forward.
-                       state <= {state[1], state[0], state[2]};

        end
 
        MandelUnit mu0(
        end
 
        MandelUnit mu0(


@@ -423,8 +426,6 @@ module MandelTop(
        wire [2:0] mandelr, mandelg, logor, logog;
        wire [1:0] mandelb, logob;
        
        wire [2:0] mandelr, mandelg, logor, logog;
        wire [1:0] mandelb, logob;
        

-       
-

        SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
        Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
        Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
        SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
        Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
        Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);