Fixed statekick once and for all, hopefully.

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index 61cb8f1d9991a72ae15261f8b2bd8781e6840108..3dc546bb9f900aad1a4e58d6fe5b9439060af7b7 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -230,11 +230,6 @@ module Mandelbrot(
        
        reg [2:0] state = 3'b001;       // One-hot encoded state.
        
-       // On pixclk = 1,
-       //    A new value to be loaded comes in, and a value in need of loopback comes out.
-       // On pixclk = 0,
-       //    A new value in need of loopback comes in, and a completed value comes out.
-       
        assign initx = state[0] ? rx :
                       state[1] ? stagex[1] :
                       stagex[2];
@@ -263,34 +258,34 @@ module Mandelbrot(
                       state[1] ? stageb[1] :
                       stageb[2];
        assign initci = state[0] ? 8'b00000000 :
-                       state[1] ? stageb[1] : 
-                       stageb[2];
+                       state[1] ? stageci[1] : 
+                       stageci[2];
        
        reg [7:0] out;
-       reg typethea = 0;       // Whether we have typed the A.
-       reg statekick = 0;      // State needs to be kicked back to 3'b010 on the next mclk.
-
-       // This is guaranteed to converge after two pixclks.
-       //always @(negedge mclk)
-       //      if (pixclk && !typethea) begin
-       //              typethea <= 1;
-       //              statekick <= 1;
-       //      end else if (typethea) begin // This is the edge of the falling anus.
-       //              typethea <= 0;
-       //              statekick <= 0;
-       //      end
+       
+       // We detect when the state should be poked by a high negedge followed
+       // by a high posedge -- if tha thappens, then we're guaranteed that the
+       // state following the current state will be 100.
+       reg lastneg;
+       always @(negedge mclk)
+               lastneg <= pixclk;
        
        always @(posedge mclk)
        begin
+               if (lastneg && pixclk)  // If a pixclk has happened, the state should be reset.
+                       state <= 3'b100;
+               else                                            // Otherwise, just poke it forward.
+                       state <= {state[1], state[0], state[2]};
+       
                // Data output handling
                if (state[0]) begin
                        {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
                end
-               if (state[2]) begin
+               if (state[1]) begin
                        out <= ~mb[`MAXOUTN] + colorofs;
                end
                
-               if (state[1]) begin             // PnR0 in, PnR2 out
+               if (state[0]) begin             // PnR0 in, PnR2 out
                        stagex[2] <= xprop[`MAXOUTN];
                        stagey[2] <= yprop[`MAXOUTN];
                        stager[2] <= mr[`MAXOUTN];
@@ -303,7 +298,7 @@ module Mandelbrot(
                        stageci[2] <= curiter[`MAXOUTN];
                end
                
-               if (state[0]) begin     // PnR2 in, PnR1 out
+               if (state[2]) begin     // PnR2 in, PnR1 out
                        stagex[1] <= xprop[`MAXOUTN];
                        stagey[1] <= yprop[`MAXOUTN];
                        stager[1] <= mr[`MAXOUTN];
@@ -315,11 +310,6 @@ module Mandelbrot(
                        stageb[1] <= mb[`MAXOUTN];
                        stageci[1] <= curiter[`MAXOUTN];
                end
-               
-               if (statekick)          // If a pixclk has happened, the state should be reset.
-                       state <= 3'b010;
-               else                                            // Otherwise, just poke it forward.
-                       state <= {state[1], state[0], state[2]};
        end
 
        MandelUnit mu0(
@@ -396,21 +386,28 @@ module MandelTop(
 
        wire pixclk, mclk, gclk2, clk;
        wire dcm1ok, dcm2ok;
-       assign dcmok = dcm1ok && dcm2ok;
+       //assign dcmok = dcm1ok && dcm2ok;
+       
+       //IBUFG typeA(.O(clk), .I(gclk));
        
-       IBUFG typeA(.O(clk), .I(gclk));
+       //pixDCM dcm(                                   // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+       //      .CLKIN_IN(clk), 
+       //      .CLKFX_OUT(pixclk),
+       //      .LOCKED_OUT(dcm1ok)
+       //      );
        
-       pixDCM dcm(                                     // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
-               .CLKIN_IN(clk), 
-               .CLKFX_OUT(pixclk),
-               .LOCKED_OUT(dcm1ok)
-               );
+       //mandelDCM dcm2(
+       //      .CLKIN_IN(clk),
+       //      .CLKFX_OUT(mclk),
+       //      .LOCKED_OUT(dcm2ok)
+       //      );
        
-       mandelDCM dcm2(
-               .CLKIN_IN(clk),
-               .CLKFX_OUT(mclk),
-               .LOCKED_OUT(dcm2ok)
-               );
+       mainDCM dcm (
+    .U1_CLKIN_IN(gclk), 
+    .U1_CLKDV_OUT(pixclk), 
+    .U2_CLKFX_OUT(mclk), 
+    .U2_LOCKED_OUT(dcmok)
+    );
        
        wire border;
        wire [11:0] x, y;