Optimization baseline, 77.788MHz, 4894 Slices, 1849 slice FFs, 9078 LUTs

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index 306c8a75ba23b6da4790bc97c62430dd436cca52..42e614a08f7d524a1576cfb2c13ae344c33ce85a 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -1,4 +1,4 @@
-/*
+/* 
  * MandelFPGA
  * by Joshua Wise and Chris Lu
  * 
@@ -113,6 +113,7 @@ module MandelUnit(
        output reg [7:0] obail, ocuriter);
 
        wire [14:0] r2, i2, ri, diff;
+       wire [15:0] twocdiff;
        wire r2sign, i2sign, risign, dsign;
        wire [16:0] bigsum;
        wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
@@ -132,8 +133,9 @@ module MandelUnit(
        assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
        assign rin_ovf = rd;
        assign iin_ovf = id;
-       assign diff = (r2 > i2) ? r2 - i2 : i2 - r2;
-       assign dsign = (r2 > i2) ? 0 : 1;
+       assign twocdiff = r2 - i2;
+       assign diff = twocdiff[15] ? -twocdiff : twocdiff;
+       assign dsign = twocdiff[15];
 
        always @ (posedge clk)
        begin