Remove the DCM cascade unit -- makes it faster to synthesize

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index ad8e90c98bf55a0fb261304960929116050da8c0..40eac0b8eb659e6cc5b0ea1fbcab45f696397f34 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -262,19 +262,21 @@ module Mandelbrot(
                        stageci[2];
        
        reg [7:0] out;
-       reg typethea = 0;       // Whether we have typed the A.
-       reg statekick = 0;      // State needs to be kicked back to 3'b010 on the next mclk.
-
-       // This is guaranteed to converge after two pixclks.
+       
+       // We detect when the state should be poked by a high negedge followed
+       // by a high posedge -- if tha thappens, then we're guaranteed that the
+       // state following the current state will be 100.
+       reg lastneg;
        always @(negedge mclk)
-               if (pixclk && !statekick) begin
-                       statekick <= 1;
-               end else if (statekick) begin // This is the edge of the falling anus.
-                       statekick <= 0;
-               end
+               lastneg <= pixclk;
        
        always @(posedge mclk)
        begin
+               if (lastneg && pixclk)  // If a pixclk has happened, the state should be reset.
+                       state <= 3'b100;
+               else                                            // Otherwise, just poke it forward.
+                       state <= {state[1], state[0], state[2]};
+       
                // Data output handling
                if (state[0]) begin
                        {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
@@ -308,11 +310,6 @@ module Mandelbrot(
                        stageb[1] <= mb[`MAXOUTN];
                        stageci[1] <= curiter[`MAXOUTN];
                end
-               
-               if (statekick)          // If a pixclk has happened, the state should be reset.
-                       state <= 3'b010;
-               else                                            // Otherwise, just poke it forward.
-                       state <= {state[1], state[0], state[2]};
        end
 
        MandelUnit mu0(
@@ -389,28 +386,21 @@ module MandelTop(
 
        wire pixclk, mclk, gclk2, clk;
        wire dcm1ok, dcm2ok;
-       //assign dcmok = dcm1ok && dcm2ok;
-       
-       //IBUFG typeA(.O(clk), .I(gclk));
+       assign dcmok = dcm1ok && dcm2ok;
        
-       //pixDCM dcm(                                   // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
-       //      .CLKIN_IN(clk), 
-       //      .CLKFX_OUT(pixclk),
-       //      .LOCKED_OUT(dcm1ok)
-       //      );
+       IBUFG typeA(.O(clk), .I(gclk));
        
-       //mandelDCM dcm2(
-       //      .CLKIN_IN(clk),
-       //      .CLKFX_OUT(mclk),
-       //      .LOCKED_OUT(dcm2ok)
-       //      );
+       pixDCM dcm(                                     // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+               .CLKIN_IN(clk), 
+               .CLKFX_OUT(pixclk),
+               .LOCKED_OUT(dcm1ok)
+               );
        
-       mainDCM dcm (
-    .U1_CLKIN_IN(gclk), 
-    .U1_CLKDV_OUT(pixclk), 
-    .U2_CLKFX_OUT(mclk), 
-    .U2_LOCKED_OUT(dcmok)
-    );
+       mandelDCM dcm2(
+               .CLKIN_IN(clk),
+               .CLKFX_OUT(mclk),
+               .LOCKED_OUT(dcm2ok)
+               );
        
        wire border;
        wire [11:0] x, y;