Holy crap, dropped lut count to 7640, and slice count to 4253

[mandelfpga.git] / Main.v

diff --git a/Main.v b/Main.v
index 2dd47640f4aabc4a22a334e689165f76a70646e4..0c1e6dce60bd1927c8620af7357ce7266818b0be 100644 (file)
--- a/Main.v
+++ b/Main.v
@@ -1,4 +1,4 @@
-/*
+/* 

  * MandelFPGA
  * by Joshua Wise and Chris Lu
  * 
  * MandelFPGA
  * by Joshua Wise and Chris Lu
  * 


@@ -8,7 +8,7 @@
 
 `define XRES 640
 `define YRES 480
 
 `define XRES 640
 `define YRES 480

-`define WHIRRRRR 21
+`define WHIRRRRR 27

 
 module SyncGen(
        input pixclk,
 
 module SyncGen(
        input pixclk,


@@ -64,24 +64,24 @@ module NaiveMultiplier(
        input xsign, ysign,
        output reg [12:0] out,
        output reg sign,
        input xsign, ysign,
        output reg [12:0] out,
        output reg sign,

-       output reg [1:0] ovf);
+       output reg ovf);

 
        always @(posedge clk)
        begin
                {ovf,out} <=
 
        always @(posedge clk)
        begin
                {ovf,out} <=

-                       (((y[12] ? (x     ) : 0)  +
-                         (y[11] ? (x >> 1) : 0)  +
-                         (y[10] ? (x >> 2) : 0)  +
-                         (y[9]  ? (x >> 3) : 0)) +
-                        ((y[8]  ? (x >> 4) : 0)  +
-                         (y[7]  ? (x >> 5) : 0)  +
-                         (y[6]  ? (x >> 6) : 0)))+
-                       (((y[5]  ? (x >> 7) : 0)  +
-                         (y[4]  ? (x >> 8) : 0)  +
-                         (y[3]  ? (x >> 9) : 0)) +
-                        ((y[2]  ? (x >> 10): 0)  +
-                         (y[1]  ? (x >> 11): 0)  +
-                         (y[0]  ? (x >> 12): 0)));
+                       (((y[12] ? (x       ) : 0)   +
+                         (y[11] ? (x[12:1]) : 0)   +
+                         (y[10] ? (x[12:2]) : 0))  +
+                       (((y[9]  ? (x[12:3]) : 0)   +
+                         (y[8]  ? (x[12:4]) : 0))  +
+                        ((y[7]  ? (x[12:5]) : 0)   +
+                         (y[6]  ? (x[12:6]) : 0))))+
+                       (((y[5]  ? (x[12:7]) : 0)   +
+                         (y[4]  ? (x[12:8]) : 0)   +
+                         (y[3]  ? (x[12:9]) : 0))  +
+                        ((y[2]  ? (x[12:10]): 0)   +
+                         (y[1]  ? (x[12:11]): 0)   +
+                         (y[0]  ? (x[12]): 0)));

                sign <= xsign ^ ysign;
        end
 
                sign <= xsign ^ ysign;
        end
 


@@ -89,36 +89,39 @@ endmodule
 
 module Multiplier(
        input clk,
 
 module Multiplier(
        input clk,

-       input [11:0] x, y,
+       input [12:0] x, y,

        input xsign, ysign,
        input xsign, ysign,

-       output wire [11:0] out,
+       output wire [12:0] out,

        output wire sign,
        output wire sign,

-       output wire [1:0] overflow);
+       output wire overflow);

 
        NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
 
 endmodule
 
 
        NaiveMultiplier nm(clk, x, y, xsign, ysign, out, sign, overflow);
 
 endmodule
 

+// Yuq.

 module MandelUnit(
        input clk,
        input [12:0] x, y,
        input xsign, ysign,
 module MandelUnit(
        input clk,
        input [12:0] x, y,
        input xsign, ysign,

-       input [13:0] r, i,
+       input [14:0] r, i,

        input rsign, isign,
        input [7:0] ibail, icuriter,
        output reg [12:0] xout, yout,
        output reg xsout, ysout,
        input rsign, isign,
        input [7:0] ibail, icuriter,
        output reg [12:0] xout, yout,
        output reg xsout, ysout,

-       output reg [13:0] rout, iout,
+       output reg [14:0] rout, iout,

        output reg rsout, isout,
        output reg [7:0] obail, ocuriter);
 
        output reg rsout, isout,
        output reg [7:0] obail, ocuriter);
 

-       wire [13:0] r2, i2, ri, diff;
+       wire [13:0] r2, i2;
+       wire [14:0] ri, diff;
+       wire [15:0] twocdiff;

        wire r2sign, i2sign, risign, dsign;
        wire r2sign, i2sign, risign, dsign;

-       wire [16:0] bigsum;
-       wire bigsum_ovf, rin_ovf, iin_ovf, throwaway;
+       wire [14:0] bigsum;
+       wire bigsum_ovf;

 
        reg [12:0] xd, yd;
 
        reg [12:0] xd, yd;

-       reg rd, id;
+       reg ineedbaild;

        reg xsd, ysd;
        reg [7:0] ibaild, curiterd;
 
        reg xsd, ysd;
        reg [7:0] ibaild, curiterd;
 


@@ -126,14 +129,47 @@ module MandelUnit(
 
        Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
        Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);
 
        Multiplier r2m(clk, r[12:0], r[12:0], rsign, rsign, r2[12:0], r2sign, r2[13]);
        Multiplier i2m(clk, i[12:0], i[12:0], isign, isign, i2[12:0], i2sign, i2[13]);

-       Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, throwaway);
+       Multiplier rim(clk, r[12:0], i[12:0], rsign, isign, ri[13:1], risign, ri[14]);

 
 

-       assign bigsum = r2 + i2;
-       assign bigsum_ovf = bigsum[16] | bigsum[15] | bigsum[14];
-       assign rin_ovf = rd;
-       assign iin_ovf = id;
-       assign diff = (r2 > i2) ? r2 - i2 : i2 - r2;
-       assign dsign = (r2 > i2) ? 0 : 1;
+       assign bigsum = r2[13:0] + i2[13:0];
+       wire shnasto = bigsum[14];
+       wire shnasto2 =         // o shi
+               ((r[13] & i[13]) |
+               ((r[13] ^ i[13]) &
+               ((r[12] & i[12]) |
+               ((r[12] ^ i[12]) &
+               ((r[11] & i[11]) |
+               ((r[11] ^ i[11]) &
+               ((r[10] & i[10]) |
+               ((r[10] ^ i[10]) &
+               ((r[ 9] & i[ 9]) |
+               ((r[ 9] ^ i[ 9]) &
+               ((r[ 8] & i[ 8]) |
+               ((r[ 8] ^ i[ 8]) &
+               ((r[ 7] & i[ 7]) |
+               ((r[ 7] ^ i[ 7]) &
+               ((r[ 6] & i[ 6]) |
+               ((r[ 6] ^ i[ 6]) &
+               ((r[ 5] & i[ 5]) |
+               ((r[ 5] ^ i[ 5]) &
+               ((r[ 4] & i[ 4]) |
+               ((r[ 4] ^ i[ 4]) &
+               ((r[ 3] & i[ 3]) |
+               ((r[ 3] ^ i[ 3]) &
+               ((r[ 2] & i[ 2]) |
+               ((r[ 2] ^ i[ 2]) &
+               ((r[ 1] & i[ 1]) |
+               ((r[ 1] ^ i[ 1]) &
+                (r[ 0] & i[ 0])
+               ))))))))))))))))))))))))));
+       assign bigsum_ovf = shnasto;
+       
+       assign twocdiff = r2 - i2;
+       assign diff = twocdiff[15] ? -twocdiff : twocdiff;
+       assign dsign = twocdiff[15];
+       
+       wire [15:0] twocrout = xd - diff;
+       wire [15:0] twociout = yd - ri;

 
        always @ (posedge clk)
        begin
 
        always @ (posedge clk)
        begin


@@ -147,28 +183,29 @@ module MandelUnit(
                ysout <= ysd;
                ibaild <= ibail;
                curiterd <= icuriter;
                ysout <= ysd;
                ibaild <= ibail;
                curiterd <= icuriter;

-               rd <= r[13];
-               id <= i[13];
+               ineedbaild <= r[13] | r[14] | i[13] | i[14];

 
 

+               // r^2 - i^2 + x

                if (xsd ^ dsign) begin
                if (xsd ^ dsign) begin

-                       if (diff > xd) begin
-                               rout <= diff - xd;
+                       if (twocrout[15]) begin // diff > xd
+                               rout <= -twocrout;

                                rsout <= dsign;
                        end else begin
                                rsout <= dsign;
                        end else begin

-                               rout <= xd - diff;
+                               rout <= twocrout;

                                rsout <= xsd;
                        end
                end else begin
                        rout <= diff + xd;
                                rsout <= xsd;
                        end
                end else begin
                        rout <= diff + xd;

-                       rsout <= xsd;
+                       rsout <= xsd;   // xsd == dsign

                end
                
                end
                

+               // 2 * r * i + y

                if (ysd ^ risign) begin
                if (ysd ^ risign) begin

-                       if (ri > yd) begin
-                               iout <= ri - yd;
+                       if (twociout[15]) begin // ri > yd
+                               iout <= -twociout;

                                isout <= risign;
                        end else begin
                                isout <= risign;
                        end else begin

-                               iout <= yd - ri;
+                               iout <= twociout;

                                isout <= ysd;
                        end
                end else begin
                                isout <= ysd;
                        end
                end else begin


@@ -178,7 +215,7 @@ module MandelUnit(
                
                // If we haven't bailed out, and we meet any of the bailout conditions,
                // bail out now.  Otherwise, leave the bailout at whatever it was before.
                
                // If we haven't bailed out, and we meet any of the bailout conditions,
                // bail out now.  Otherwise, leave the bailout at whatever it was before.

-               if ((ibaild == 255) && (bigsum_ovf | rin_ovf | iin_ovf))
+               if ((ibaild == 255) && (bigsum_ovf | ineedbaild))

                        obail <= curiterd;
                else
                        obail <= ibaild;
                        obail <= curiterd;
                else
                        obail <= ibaild;


@@ -191,10 +228,12 @@ module Mandelbrot(
        input mclk,
        input pixclk,
        input [11:0] x, y,
        input mclk,
        input pixclk,
        input [11:0] x, y,

-       input [12:0] xofs, yofs,
+       input [13:0] xofs, yofs,

        input [7:0] colorofs,
        input [2:0] scale,
        output reg [2:0] red, green, output reg [1:0] blue);
        input [7:0] colorofs,
        input [2:0] scale,
        output reg [2:0] red, green, output reg [1:0] blue);

+
+`define MAXOUTN 11

        
        wire [12:0] rx, ry;
        wire [13:0] nx, ny;
        
        wire [12:0] rx, ry;
        wire [13:0] nx, ny;


@@ -206,64 +245,114 @@ module Mandelbrot(
        assign rxsign = nx[13];
        assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
        assign rysign = ny[13];
        assign rxsign = nx[13];
        assign ry = (ny[13] ? -ny[12:0] : ny[12:0]) << scale;
        assign rysign = ny[13];

-       

 
 

-       wire [13:0] mr[9:0], mi[9:0];
-       wire mrs[9:0], mis[9:0];
-       wire [7:0] mb[9:0];
-       wire [12:0] xprop[9:0], yprop[9:0];
-       wire xsprop[9:0], ysprop[9:0];
-       wire [7:0] curiter[9:0];
+       wire [14:0] mr[`MAXOUTN:0], mi[`MAXOUTN:0];
+       wire mrs[`MAXOUTN:0], mis[`MAXOUTN:0];
+       wire [7:0] mb[`MAXOUTN:0];
+       wire [12:0] xprop[`MAXOUTN:0], yprop[`MAXOUTN:0];
+       wire xsprop[`MAXOUTN:0], ysprop[`MAXOUTN:0];
+       wire [7:0] curiter[`MAXOUTN:0];

        
        

-       wire [13:0] initx, inity, initr, initi;
-       wire [7:0] initci, initb;
-       wire initxs, initys, initrs, initis;
+       reg [14:0] initx, inity, initr, initi;
+       reg [7:0] initci, initb;
+       reg initxs, initys, initrs, initis;

        
        

-       reg [13:0] loopx, loopy, loopr, loopi;
-       reg [7:0] loopci, loopb;
-       reg loopxs, loopys, looprs, loopis;
+       // Values after the number of iterations denoted by the subscript.
+       reg [14:0] stagex [2:1], stagey [2:1], stager [2:1], stagei [2:1];
+       reg [7:0] stageci [2:1], stageb [2:1];
+       reg stagexs [2:1], stageys [2:1], stagers [2:1], stageis [2:1];

        
        

-       reg state = 0;
+       reg [2:0] state = 3'b001;       // One-hot encoded state.

        
        

-       // On pixclk = 1,
-       //    A new value to be loaded comes in, and a value in need of loopback comes out.
-       // On pixclk = 0,
-       //    A new value in need of loopback comes in, and a completed value comes out.
-       
-       assign initx = state ? rx : loopx;
-       assign inity = state ? ry : loopy;
-       assign initr = state ? rx : loopr;
-       assign initi = state ? ry : loopi;
-       assign initxs = state ? rxsign : loopxs;
-       assign initys = state ? rysign : loopys;
-       assign initrs = state ? rxsign : looprs;
-       assign initis = state ? rysign : loopis;
-       assign initb = state ? 8'b11111111 : loopb;
-       assign initci = state ? 8'b00000000 : loopci;
+       // States are advanced one from what they should be, so that they'll
+       // get there on the _next_ mclk.
+       always @(posedge mclk)
+       begin
+               initx <= (state[2]) ? rx :
+                   (state[0]) ? stagex[1] :
+                   (state[1]) ? stagex[2] : 0;
+               inity <= (state[2]) ? ry :
+                      (state[0]) ? stagey[1] :
+                      (state[1]) ? stagey[2] : 0;
+               initr <= (state[2]) ? rx :
+                      (state[0]) ? stager[1] :
+                      (state[1]) ? stager[2] : 0;
+               initi <= (state[2]) ? ry :
+                      (state[0]) ? stagei[1] :
+                      (state[1]) ? stagei[2] : 0;
+               initxs <= (state[2]) ? rxsign :
+                       (state[0]) ? stagexs[1] :
+                       (state[1]) ? stagexs[2] : 0;
+               initys <= (state[2]) ? rysign :
+                       (state[0]) ? stageys[1] :
+                       (state[1]) ? stageys[2] : 0;
+               initrs <= (state[2]) ? rxsign :
+                       (state[0]) ? stagers[1] :
+                       (state[1]) ? stagers[2] : 0;
+               initis <= (state[2]) ? rysign :
+                       (state[0]) ? stageis[1] :
+                       (state[1]) ? stageis[2] : 0;
+               initb <= (state[2]) ? 8'b11111111 :
+                      (state[0]) ? stageb[1] :
+                      (state[1]) ? stageb[2] : 0;
+               initci <= (state[2]) ? 8'b00000000 :
+                       (state[0]) ? stageci[1] : 
+                       (state[1]) ? stageci[2] : 0;
+       end

        
        reg [7:0] out;
        
        reg [7:0] out;

-       reg pixclksync;
+       
+       // We detect when the state should be poked by a high negedge followed
+       // by a high posedge -- if that happens, then we're guaranteed that the
+       // state following the current state will be 3'b100.
+       reg lastneg;

        always @(negedge mclk)
        always @(negedge mclk)

-               pixclksync <= ~pixclk;
+               lastneg <= pixclk;

        
        always @(posedge mclk)
        begin
        
        always @(posedge mclk)
        begin

-               if (!state) begin
-                       out <= ~mb[9] + colorofs;
-               end else begin
+               if (lastneg && pixclk)  // If a pixclk has happened, the state should be reset.
+                       state <= 3'b100;
+               else                                            // Otherwise, just poke it forward.
+                       case(state)
+                       3'b001: state <= 3'b010;
+                       3'b010: state <= 3'b100;
+                       3'b100: state <= 3'b001;
+                       endcase
+       
+               // Data output handling
+               if (state[0]) begin

                        {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};
                        {red, green, blue} <= {out[0],out[3],out[6],out[1],out[4],out[7],out[2],out[5]};

-                       loopx <= xprop[9];
-                       loopy <= yprop[9];
-                       loopr <= mr[9];
-                       loopi <= mi[9];
-                       loopxs <= xsprop[9];
-                       loopys <= ysprop[9];
-                       looprs <= mrs[9];
-                       loopis <= mis[9];
-                       loopb <= mb[9];
-                       loopci <= curiter[9];

                end
                end

-               state <= ~pixclksync;
+               if (state[1]) begin
+                       out <= ~mb[`MAXOUTN] + colorofs;
+               end
+               
+               if (state[0]) begin             // PnR0 in, PnR2 out
+                       stagex[2] <= xprop[`MAXOUTN];
+                       stagey[2] <= yprop[`MAXOUTN];
+                       stager[2] <= mr[`MAXOUTN];
+                       stagei[2] <= mi[`MAXOUTN];
+                       stagexs[2] <= xsprop[`MAXOUTN];
+                       stageys[2] <= ysprop[`MAXOUTN];
+                       stagers[2] <= mrs[`MAXOUTN];
+                       stageis[2] <= mis[`MAXOUTN];
+                       stageb[2] <= mb[`MAXOUTN];
+                       stageci[2] <= curiter[`MAXOUTN];
+               end
+               
+               if (state[2]) begin     // PnR2 in, PnR1 out
+                       stagex[1] <= xprop[`MAXOUTN];
+                       stagey[1] <= yprop[`MAXOUTN];
+                       stager[1] <= mr[`MAXOUTN];
+                       stagei[1] <= mi[`MAXOUTN];
+                       stagexs[1] <= xsprop[`MAXOUTN];
+                       stageys[1] <= ysprop[`MAXOUTN];
+                       stagers[1] <= mrs[`MAXOUTN];
+                       stageis[1] <= mis[`MAXOUTN];
+                       stageb[1] <= mb[`MAXOUTN];
+                       stageci[1] <= curiter[`MAXOUTN];
+               end

        end
 
        MandelUnit mu0(
        end
 
        MandelUnit mu0(


@@ -274,35 +363,23 @@ module Mandelbrot(
                xprop[0], yprop[0], xsprop[0], ysprop[0],
                mr[0], mi[0], mrs[0], mis[0],
                mb[0], curiter[0]);
                xprop[0], yprop[0], xsprop[0], ysprop[0],
                mr[0], mi[0], mrs[0], mis[0],
                mb[0], curiter[0]);

+               
+`define MAKE_UNIT(name, num) \
+       MandelUnit name(mclk, \
+               xprop[(num)], yprop[(num)], xsprop[(num)], ysprop[(num)], mr[(num)], mi[(num)], mrs[(num)], mis[(num)], mb[(num)], curiter[(num)], \
+               xprop[(num)+1], yprop[(num)+1], xsprop[(num)+1], ysprop[(num)+1], mr[(num)+1], mi[(num)+1], mrs[(num)+1], mis[(num)+1], mb[(num)+1], curiter[(num)+1])

 
 

-       MandelUnit mu1(mclk,
-               xprop[0], yprop[0], xsprop[0], ysprop[0], mr[0], mi[0], mrs[0], mis[0], mb[0], curiter[0],
-               xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1]);
-       MandelUnit mu2(mclk,
-               xprop[1], yprop[1], xsprop[1], ysprop[1], mr[1], mi[1], mrs[1], mis[1], mb[1], curiter[1],
-               xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2]);
-       MandelUnit mu3(mclk,
-               xprop[2], yprop[2], xsprop[2], ysprop[2], mr[2], mi[2], mrs[2], mis[2], mb[2], curiter[2],
-               xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3]);
-       MandelUnit mu4(mclk,
-               xprop[3], yprop[3], xsprop[3], ysprop[3], mr[3], mi[3], mrs[3], mis[3], mb[3], curiter[3],
-               xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4]);
-       MandelUnit mu5(mclk,
-               xprop[4], yprop[4], xsprop[4], ysprop[4], mr[4], mi[4], mrs[4], mis[4], mb[4], curiter[4],
-               xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5]);
-       MandelUnit mu6(mclk,
-               xprop[5], yprop[5], xsprop[5], ysprop[5], mr[5], mi[5], mrs[5], mis[5], mb[5], curiter[5],
-               xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6]);
-       MandelUnit mu7(mclk,
-               xprop[6], yprop[6], xsprop[6], ysprop[6], mr[6], mi[6], mrs[6], mis[6], mb[6], curiter[6],
-               xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7]);
-       MandelUnit mu8(mclk,
-               xprop[7], yprop[7], xsprop[7], ysprop[7], mr[7], mi[7], mrs[7], mis[7], mb[7], curiter[7],
-               xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8]);
-       MandelUnit mu9(mclk,
-               xprop[8], yprop[8], xsprop[8], ysprop[8], mr[8], mi[8], mrs[8], mis[8], mb[8], curiter[8],
-               xprop[9], yprop[9], xsprop[9], ysprop[9], mr[9], mi[9], mrs[9], mis[9], mb[9], curiter[9]);
-       
+       `MAKE_UNIT(mu1, 0);
+       `MAKE_UNIT(mu2, 1);
+       `MAKE_UNIT(mu3, 2);
+       `MAKE_UNIT(mu4, 3);
+       `MAKE_UNIT(mu5, 4);
+       `MAKE_UNIT(mu6, 5);
+       `MAKE_UNIT(mu7, 6);
+       `MAKE_UNIT(mu8, 7);
+       `MAKE_UNIT(mu9, 8);
+       `MAKE_UNIT(mua, 9);
+       `MAKE_UNIT(mub, 10);

 endmodule
 
 module Logo(
 endmodule
 
 module Logo(


@@ -331,12 +408,27 @@ module MandelTop(
        input left, right, up, down, rst, cycle, logooff,
        input [2:0] scale);
 
        input left, right, up, down, rst, cycle, logooff,
        input [2:0] scale);
 

+       wire pixclk, mclk, clk;
+       wire dcm1ok, dcm2ok;
+       assign dcmok = dcm1ok && dcm2ok;
+       
+       IBUFG iclkbuf(.O(clk), .I(gclk));
+       
+       pixDCM dcm(                                     // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
+               .CLKIN_IN(clk), 
+               .CLKFX_OUT(pixclk),
+               .LOCKED_OUT(dcm1ok)
+               );
+       
+       mandelDCM dcm2(
+               .CLKIN_IN(clk),
+               .CLKFX_OUT(mclk),
+               .LOCKED_OUT(dcm2ok)
+               );
+       

        wire border;
        wire border;

-       wire pixclk;
-       wire [7:0] zero = 8'b0;
-       wire clk;

        wire [11:0] x, y;
        wire [11:0] x, y;

-       reg [12:0] xofs = -`XRES/2, yofs = -`YRES/2;
+       reg [13:0] xofs = -`XRES/2, yofs = -`YRES/2;

        reg [5:0] slowctr = 0;
        reg [7:0] colorcycle = 0;
        wire [11:0] realx, realy;
        reg [5:0] slowctr = 0;
        reg [7:0] colorcycle = 0;
        wire [11:0] realx, realy;


@@ -345,15 +437,8 @@ module MandelTop(
        wire [2:0] mandelr, mandelg, logor, logog;
        wire [1:0] mandelb, logob;
        
        wire [2:0] mandelr, mandelg, logor, logog;
        wire [1:0] mandelb, logob;
        

-       pixDCM dcm(                                     // CLKIN is 50MHz xtal, CLKFX_OUT is 25MHz
-               .CLKIN_IN(gclk), 
-               .CLKFX_OUT(pixclk),
-               .CLKIN_IBUFG_OUT(clk),
-               .LOCKED_OUT(dcmok)
-               );
-

        SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);
        SyncGen sync(pixclk, vs, hs, x, y, realx, realy, border);

-       Mandelbrot mandel(clk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);
+       Mandelbrot mandel(mclk, pixclk, x, y, xofs, yofs, cycle ? colorcycle : 0, scale, mandelr, mandelg, mandelb);

        Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
        
        assign {red,green,blue} =
        Logo logo(pixclk, realx, realy, logoenb, logor, logog, logob);
        
        assign {red,green,blue} =