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1 | //////////////////////////////////////////////////////////////////////////////// |
2 | // Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. | |
3 | //////////////////////////////////////////////////////////////////////////////// | |
4 | // ____ ____ | |
5 | // / /\/ / | |
6 | // /___/ \ / Vendor: Xilinx | |
7 | // \ \ \/ Version : 10.1 | |
8 | // \ \ Application : xaw2verilog | |
9 | // / / Filename : pixDCM.v | |
10 | // /___/ /\ Timestamp : 03/27/2008 18:06:47 | |
11 | // \ \ / \ | |
12 | // \___\/\___\ | |
13 | // | |
14 | //Command: xaw2verilog -intstyle /home/joshua/projects/fpga/MandelFPGA/pixDCM.xaw -st pixDCM.v | |
15 | //Design Name: pixDCM | |
16 | //Device: xc3s500e-5fg320 | |
17 | // | |
18 | // Module pixDCM | |
19 | // Generated by Xilinx Architecture Wizard | |
20 | // Written for synthesis tool: XST | |
21 | // Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI | |
22 | // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.03 ns | |
23 | `timescale 1ns / 1ps | |
24 | ||
25 | module pixDCM(CLKIN_IN, | |
26 | CLKFX_OUT, | |
27 | LOCKED_OUT); | |
28 | ||
29 | input CLKIN_IN; | |
30 | output CLKFX_OUT; | |
31 | output LOCKED_OUT; | |
32 | ||
33 | wire CLKFX_BUF; | |
34 | wire GND_BIT; | |
35 | ||
36 | assign GND_BIT = 0; | |
37 | BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), | |
38 | .O(CLKFX_OUT)); | |
39 | DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), | |
40 | .CLKIN(CLKIN_IN), | |
41 | .DSSEN(GND_BIT), | |
42 | .PSCLK(GND_BIT), | |
43 | .PSEN(GND_BIT), | |
44 | .PSINCDEC(GND_BIT), | |
45 | .RST(GND_BIT), | |
46 | .CLKDV(), | |
47 | .CLKFX(CLKFX_BUF), | |
48 | .CLKFX180(), | |
49 | .CLK0(), | |
50 | .CLK2X(), | |
51 | .CLK2X180(), | |
52 | .CLK90(), | |
53 | .CLK180(), | |
54 | .CLK270(), | |
55 | .LOCKED(LOCKED_OUT), | |
56 | .PSDONE(), | |
57 | .STATUS()); | |
58 | defparam DCM_SP_INST.CLK_FEEDBACK = "NONE"; | |
59 | defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; | |
60 | defparam DCM_SP_INST.CLKFX_DIVIDE = 4; | |
61 | defparam DCM_SP_INST.CLKFX_MULTIPLY = 2; | |
62 | defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; | |
63 | defparam DCM_SP_INST.CLKIN_PERIOD = 20.000; | |
64 | defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; | |
65 | defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; | |
66 | defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; | |
67 | defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; | |
68 | defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; | |
69 | defparam DCM_SP_INST.FACTORY_JF = 16'hC080; | |
70 | defparam DCM_SP_INST.PHASE_SHIFT = 0; | |
71 | defparam DCM_SP_INST.STARTUP_WAIT = "FALSE"; | |
72 | endmodule |