LD{D,I} A,(HL) and LD{D,I} (HL),A

diff --git a/FPGABoy.ise b/FPGABoy.ise
index d632f1ea23bf7e2ccd1682d46d44f0234fd70383..c05d0ea731329d33db5981eda7f126771ba33eac 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1d06b12f1bfd3cd10d752cd166e0d8a195c1d9d8..b7994ae3ce4fea35f6d54ed170c8385bdf8d4e59 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -31,6 +31,8 @@
 `define INSN_PUSH_reg          8'b11xx0101
 `define INSN_POP_reg                   8'b11xx0001
 `define INSN_LDH_AC                    8'b111x0010     // Either LDH A,(C) or LDH (C),A
 `define INSN_PUSH_reg          8'b11xx0101
 `define INSN_POP_reg                   8'b11xx0001
 `define INSN_LDH_AC                    8'b111x0010     // Either LDH A,(C) or LDH (C),A

+`define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
+

 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 `define INSN_reg_C             3'b001
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 `define INSN_reg_C             3'b001


@@ -275,7 +277,7 @@ module GBZ80Core(
                                                        rd <= 1;
                                                end else begin
                                                        wr <= 1;
                                                        rd <= 1;
                                                end else begin
                                                        wr <= 1;

-                                                       wdata <= {8'hFF,registers[`REG_A]};
+                                                       wdata <= registers[`REG_A];

                                                end
                                        end
                                1: begin
                                                end
                                        end
                                1: begin


@@ -284,6 +286,23 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

+                       `INSN_LDx_AHL: begin
+                               case (cycle)
+                               0: begin
+                                               address <= {registers[`REG_H],registers[`REG_L]};
+                                               if (opcode[3]) begin    // LDx A, (HL)
+                                                       rd <= 1;
+                                               end else begin
+                                                       wr <= 1;
+                                                       wdata <= registers[`REG_A];
+                                               end
+                                       end
+                               1:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -434,6 +453,20 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

+                       `INSN_LDx_AHL: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 0;
+                                               if (opcode[3])
+                                                       registers[`REG_A] <= rdata;
+                                               {registers[`REG_H],registers[`REG_L]} <=
+                                                       opcode[4] ? // if set, LDD, else LDI
+                                                       ({registers[`REG_H],registers[`REG_L]} - 1) :
+                                                       ({registers[`REG_H],registers[`REG_L]} + 1);
+                                       end
+                               endcase
+                       end

                        endcase
                        state <= `STATE_FETCH;
                end
                        endcase
                        state <= `STATE_FETCH;
                end