LD with HLs

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 84ccd1ce09d13519dacf7b43f54436d7443833f5..2aed8f586b71ff486152dd915144f13353d888dd 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index e5a7d35e16262ccfa113e892f147e39f9260adee..738bf917a1b0a4c4ab202726e6002834127ac2ff 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -130,13 +130,42 @@ module GBZ80Core(
                                endcase
                        end
                        `INSN_HALT: begin
                                endcase
                        end
                        `INSN_HALT: begin

-                               /* XXX UNIMP */
+                               `EXEC_NEWCYCLE;
+                               /* XXX Interrupts needed for HALT. */

                        end
                        `INSN_LD_HL_reg: begin
                        end
                        `INSN_LD_HL_reg: begin

-                               /* XXX UNIMP */
+                               case (cycle)
+                               0:      begin
+                                               case (opcode[2:0])
+                                               `INSN_reg_A:    begin wdata <= registers[`REG_A]; end
+                                               `INSN_reg_B:    begin wdata <= registers[`REG_B]; end
+                                               `INSN_reg_C:    begin wdata <= registers[`REG_C]; end
+                                               `INSN_reg_D:    begin wdata <= registers[`REG_D]; end
+                                               `INSN_reg_E:    begin wdata <= registers[`REG_E]; end
+                                               `INSN_reg_H:    begin wdata <= registers[`REG_H]; end
+                                               `INSN_reg_L:    begin wdata <= registers[`REG_L]; end
+                                               endcase
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               wr <= 1; rd <= 0;
+                                       end
+                               1:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase

                        end
                        `INSN_LD_reg_HL: begin
                        end
                        `INSN_LD_reg_HL: begin

-                               /* XXX UNIMP */
+                               case(cycle)
+                               0: begin
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               wr <= 0; rd <= 1;
+                                       end
+                               1: begin
+                                               tmp <= rdata;
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase

                        end
                        `INSN_LD_reg_reg: begin
                                `EXEC_INC_PC;
                        end
                        `INSN_LD_reg_reg: begin
                                `EXEC_INC_PC;


@@ -172,13 +201,31 @@ module GBZ80Core(
                                        2: cycle <= 0;
                                        endcase
                                `INSN_HALT: begin
                                        2: cycle <= 0;
                                        endcase
                                `INSN_HALT: begin

-                                       /* XXX UNIMP */
+                                       /* Nothing needs happen here. */
+                                       /* XXX Interrupts needed for HALT. */

                                end
                                `INSN_LD_HL_reg: begin
                                end
                                `INSN_LD_HL_reg: begin

-                                       /* XXX UNIMP */
+                                       case (cycle)
+                                       0: cycle <= 1;
+                                       1: cycle <= 0;
+                                       endcase

                                end
                                `INSN_LD_reg_HL: begin
                                end
                                `INSN_LD_reg_HL: begin

-                                       /* XXX UNIMP */
+                                       case (cycle)
+                                       0:      cycle <= 1;
+                                       1:      begin
+                                                       case (opcode[5:3])
+                                                       `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
+                                                       `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
+                                                       `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
+                                                       `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
+                                                       `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
+                                                       `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
+                                                       `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                                       endcase
+                                                       cycle <= 0;
+                                               end
+                                       endcase

                                end
                                `INSN_LD_reg_reg: begin
                                        case (opcode[5:3])
                                end
                                `INSN_LD_reg_reg: begin
                                        case (opcode[5:3])

diff --git a/rom.hex b/rom.hex
index 7894cdc24084f0f1a45310572bcdb42a6b896b70..2cce52b1c2e606ed5c247d38e35d5721a49b9705 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -1,3 +1,11 @@
+// LD H, 01h
+26
+01
+// LD L, 00h
+2E
+00
+// LD B, (HL)
+46

 // LD A, 12h
 3E
 12
 // LD A, 12h
 3E
 12


@@ -6,6 +14,10 @@
 // LD L, 34h
 2E
 34
 // LD L, 34h
 2E
 34

-// LD (HL), 56h
-36
-56
+// LD (HL), B
+70
+// HALT
+76
+
+@100
+56
\ No newline at end of file