Fix flags bugs in tests 6 and 8

diff --git a/core/insn_alu_a.v b/core/insn_alu_a.v
index 5fbadeef6ad0c1ae1904a51c6aae8e6799c49f1c..36bac34c15f711abb8b8a46a54c9b2e8d1441967 100644 (file)
--- a/core/insn_alu_a.v
+++ b/core/insn_alu_a.v
@@ -33,19 +33,19 @@
                case(opcode[5:3])
                `INSN_alu_RLCA: begin
                        `_A <= {`_A[6:0],`_A[7]};
                case(opcode[5:3])
                `INSN_alu_RLCA: begin
                        `_A <= {`_A[6:0],`_A[7]};

-                       `_F <= {`_F[7:5],`_A[7],`_F[3:0]};
+                       `_F <= {3'b0,`_A[7],`_F[3:0]};

                end
                `INSN_alu_RRCA: begin
                        `_A <= {`_A[0],`_A[7:1]};
                end
                `INSN_alu_RRCA: begin
                        `_A <= {`_A[0],`_A[7:1]};

-                       `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
+                       `_F <= {3'b0,`_A[0],`_F[3:0]};

                end
                `INSN_alu_RLA: begin
                        `_A <= {`_A[6:0],`_F[4]};
                end
                `INSN_alu_RLA: begin
                        `_A <= {`_A[6:0],`_F[4]};

-                       `_F <= {`_F[7:5],`_A[7],`_F[3:0]};
+                       `_F <= {3'b0,`_A[7],`_F[3:0]};

                end
                `INSN_alu_RRA: begin
                        `_A <= {`_F[4],`_A[7:1]};
                end
                `INSN_alu_RRA: begin
                        `_A <= {`_F[4],`_A[7:1]};

-                       `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
+                       `_F <= {3'b0,`_A[0],`_F[3:0]};

                end
                `INSN_alu_DAA: begin
                        `_A <= daa_tmp[7:0];
                end
                `INSN_alu_DAA: begin
                        `_A <= daa_tmp[7:0];

diff --git a/core/insn_alu_ext.v b/core/insn_alu_ext.v
index 19855868054e8a02f02318bbcb2a2de056dd1802..5ae8fe8c96fc3b3adc2612311911c56045b7f666 100644 (file)
--- a/core/insn_alu_ext.v
+++ b/core/insn_alu_ext.v
@@ -22,7 +22,7 @@
                        tmp[7]};
 
        assign rr    = {`_F[4],tmp[7:1]};
                        tmp[7]};
 
        assign rr    = {`_F[4],tmp[7:1]};

-       assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
+       assign rrf   = {({`_F[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),

                        2'b0,
                        tmp[0]};
 
                        2'b0,
                        tmp[0]};