Fix some simulator-only bugs involving debugging/illegal states. Make rd and wr...

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 9db958fa85dc93189a0251b91d1b8cb5c600ff97..8970e5d7132861495e894b319f8f3510f85333e2 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -177,17 +177,21 @@ module GBZ80Core(
        
        reg bootstrap_enb;
        
-       wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF));  /* 0 or 1 depending on which bus */
+       wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF))   /* 0 or 1 depending on which bus */
+               `ifdef isim
+                       || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
+               `endif
+                       ;
                
        assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
        assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
        assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
        assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
        assign busdata = (bus == 0) ? bus0data : bus1data;
-       assign bus0rd = (bus == 0) ? busrd : 1'bz;
-       assign bus1rd = (bus == 1) ? busrd : 1'bz;
-       assign bus0wr = (bus == 0) ? buswr : 1'bz;
-       assign bus1wr = (bus == 1) ? buswr : 1'bz;
+       assign bus0rd = (bus == 0) ? busrd : 1'b0;
+       assign bus1rd = (bus == 1) ? busrd : 1'b0;
+       assign bus0wr = (bus == 0) ? buswr : 1'b0;
+       assign bus1wr = (bus == 1) ? buswr : 1'b0;
 
        reg ie, iedelay;
 
@@ -296,6 +300,8 @@ module GBZ80Core(
                        end
                end
                `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
+                       buswr <= 0;
+                       busrd <= 0;
                end
                endcase
        
@@ -318,7 +324,7 @@ module GBZ80Core(
                                rdata <= busdata;
                                cycle <= 0;
                        end else begin
-                               if (rd) rdata <= busdata;
+                               if (rd) rdata <= busdata;       /* Still valid because peripherals are now expected to keep it held valid. */
                                cycle <= cycle + 1;
                        end
                        if (iedelay) begin
@@ -334,6 +340,8 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
+                       if (opcode[7:0] === 8'bxxxxxxxx)
+                               $stop;
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"

diff --git a/System.v b/System.v
index ebc9be4eb6d1ed10d39723031aeb83286a983d42..95b715cd322e0806612ad899662648027a675c7a 100644 (file)
--- a/System.v
+++ b/System.v
@@ -28,13 +28,16 @@ module BootstrapROM(
        input wr, rd);
 
        reg rdlatch = 0;
+       reg [7:0] addrlatch = 0;
        reg [7:0] brom [255:0];
        initial $readmemh("bootstrap.hex", brom);
 
        wire decode = address[15:8] == 0;
-       wire [7:0] odata = brom[address[7:0]];
-       always @(posedge clk)
+       wire [7:0] odata = brom[addrlatch];
+       always @(posedge clk) begin
                rdlatch <= rd && decode;
+               addrlatch <= address[7:0];
+       end
        assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule