Fix insn_bit. HOLY SHIT THE BOOT ROM WORKS c.c

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 45870d195f581fc91d2fe6617f1200789f3ab98c..05c449ac5981f33d84b1095433821e70e3368182 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -220,18 +220,18 @@ module GBZ80Core(
                );
 
        initial begin
                );
 
        initial begin

-               registers[ 0] <= 0;
-               registers[ 1] <= 0;
-               registers[ 2] <= 0;
-               registers[ 3] <= 0;
-               registers[ 4] <= 0;
-               registers[ 5] <= 0;
-               registers[ 6] <= 0;
-               registers[ 7] <= 0;
-               registers[ 8] <= 0;
-               registers[ 9] <= 0;
-               registers[10] <= 0;
-               registers[11] <= 0;
+               `_A <= 0;
+               `_B <= 0;
+               `_C <= 0;
+               `_D <= 0;
+               `_E <= 0;
+               `_F <= 0;
+               `_H <= 0;
+               `_L <= 0;
+               `_PCH <= 0;
+               `_PCL <= 0;
+               `_SPH <= 0;
+               `_SPL <= 0;

                rd <= 1;
                wr <= 0;
                newcycle <= 1;
                rd <= 1;
                wr <= 0;
                newcycle <= 1;

diff --git a/LCDC.v b/LCDC.v
index 1f29d4aeb530c39091ab5344fed4f92465f6d2dc..7b402e4fdf7fab3d3f56a0e8e6526085320e38e8 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -145,7 +145,8 @@ module LCDC(
        reg [7:0] tileno;
        wire [10:0] tileaddr = {tileno, vypos[2:0]};
        reg [7:0] tilehigh, tilelow;
        reg [7:0] tileno;
        wire [10:0] tileaddr = {tileno, vypos[2:0]};
        reg [7:0] tilehigh, tilelow;

-       assign pixdata = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};

        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);

diff --git a/Makefile b/Makefile
index fae41fe0279c1aeb6d5ef02900c859316cf8f342..466b640ac85801f0275c3e3c7a42ed2a2ccbfb76 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -6,7 +6,8 @@ VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
        insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
        insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
        Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \
        insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
        insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
        Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \

-       insn_ldbcde_a.v insn_alu_ext.v insn_bit.v insn_two_byte.v
+       insn_ldbcde_a.v insn_alu_ext.v insn_bit.v insn_two_byte.v \
+       insn_incdec_reg8.v

 
 all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr
 
 
 all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr
 

diff --git a/bootrom.asm b/bootrom.asm
index b2a2db869afc157235ce852f77dc8f3d4796bf4b..3cdf0e9a0a7ea8d2c1adfc74af837b620bdc9caf 100644 (file)
--- a/bootrom.asm
+++ b/bootrom.asm
@@ -35,7 +35,7 @@ Addr_0027:
        CP $34          ; $0030
        JR NZ, Addr_0027        ; $0032
 
        CP $34          ; $0030
        JR NZ, Addr_0027        ; $0032
 

-       LD DE,$00d8             ; $0034  Load 8 additional bytes into Video RAM
+       LD DE,Addr_00D8         ; $0034  Load 8 additional bytes into Video RAM

        LD B,$08                ; $0037
 Addr_0039:
        LD A,[DE]               ; $0039
        LD B,$08                ; $0037
 Addr_0039:
        LD A,[DE]               ; $0039


@@ -129,7 +129,7 @@ Addr_0098:
        INC HL          ; $00a6
        RET                     ; $00a7
 
        INC HL          ; $00a6
        RET                     ; $00a7
 

-Addr_00A8:
+NintendoLogo:

        ;Nintendo Logo
        DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D 
        DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99 
        ;Nintendo Logo
        DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D 
        DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99 


@@ -143,7 +143,7 @@ Addr_00D8:
 
 Addr_00E0:     
        LD HL,$0104             ; $00e0 ; point HL to Nintendo logo in cart
 
 Addr_00E0:     
        LD HL,$0104             ; $00e0 ; point HL to Nintendo logo in cart

-       LD DE,$00a8             ; $00e3 ; point DE to Nintendo logo in DMG rom
+       LD DE,NintendoLogo      ; $00e3 ; point DE to Nintendo logo in DMG rom

 
 Addr_00E6:
        LD A,[DE]               ; $00e6
 
 Addr_00E6:
        LD A,[DE]               ; $00e6


@@ -168,3 +168,21 @@ Addr_00F4:
 
        LD A,$01                ; $00fc
        LD [$FF50],A    ; $00fe ;turn off DMG rom
 
        LD A,$01                ; $00fc
        LD [$FF50],A    ; $00fe ;turn off DMG rom

+
+
+       SECTION "b",HOME[$100]
+boot:  jr .running     ; $0100
+       nop             ; $0102
+       nop             ; $0103
+       ;Nintendo Logo  ; $0104
+       DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D 
+       DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99 
+       DB $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E
+       ;$0134 
+       DB $00,$E7,$00,$00,$00,$00,$00,$00, $00,$00,$00,$00,$00,$00,$00,$00
+       ;$0144
+       DB $00,$00,$00,$00,$00,$00,$00,$00, $00,$00,$00,$00,$00,$00,$00,$00
+.running:
+       ld a, $FF
+       ld [$FF51], A
+.diq:  jr .diq

diff --git a/diag.asm b/diag.asm
index 668452decb47fea864ee0715b5b6649a189d4b43..d269b25c1e38b186b7e9f62a700fe7fb9de181e9 100644 (file)
--- a/diag.asm
+++ b/diag.asm
@@ -91,6 +91,9 @@ tiles:
        db %00000000
 
 putscreen:
        db %00000000
 
 putscreen:

+       LD A,$fc                ; $001d  Setup BG palette
+       LD [$FF47],A    ; $001f
+

        ; Wait for vblank
        call .vblwait
 
        ; Wait for vblank
        call .vblwait
 


@@ -318,8 +321,8 @@ waitsw:
        ld a,[c]
        cp $0
        jr z,.loop1
        ld a,[c]
        cp $0
        jr z,.loop1

-.loop2:
-       ld a,[c]
+
+.loop2:        ld a,[c]

        cp $0
        jr nz,.loop2
        ret
        cp $0
        jr nz,.loop2
        ret

diff --git a/insn_bit.v b/insn_bit.v
index c4b1fe5156aa5ca039345519870889bbb71cc96f..379215e2314728844e1ca8be3ffff0610c9ccf79 100644 (file)
--- a/insn_bit.v
+++ b/insn_bit.v
@@ -5,6 +5,7 @@
                end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 2)) begin
                        `EXEC_NEWCYCLE
                end else begin
                end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 2)) begin
                        `EXEC_NEWCYCLE
                end else begin

+                       `EXEC_INC_PC

                        case (opcode[2:0])
                        `INSN_reg_A:    tmp <= `_A;
                        `INSN_reg_B:    tmp <= `_B;
                        case (opcode[2:0])
                        `INSN_reg_A:    tmp <= `_A;
                        `INSN_reg_B:    tmp <= `_B;

diff --git a/insn_ret-retcc.v b/insn_ret-retcc.v
index bad4c04d9f457df84e67b0d230cbd4d7d1008129..dab27c3ef99023b050b109758daabe7dd44fa1af 100644 (file)
--- a/insn_ret-retcc.v
+++ b/insn_ret-retcc.v
@@ -5,10 +5,10 @@
                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                                `EXEC_INC_PC    // cycle 1 is skipped if we are not retcc
                                case (opcode[4:3])
                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                                `EXEC_INC_PC    // cycle 1 is skipped if we are not retcc
                                case (opcode[4:3])

-                               `INSN_cc_NZ:    if (registers[`REG_F][7]) `EXEC_NEWCYCLE
-                               `INSN_cc_Z:     if (~registers[`REG_F][7]) `EXEC_NEWCYCLE
-                               `INSN_cc_NC:    if (registers[`REG_F][4]) `EXEC_NEWCYCLE
-                               `INSN_cc_C:     if (~registers[`REG_F][4]) `EXEC_NEWCYCLE
+                               `INSN_cc_NZ:    if (`_F[7])  `EXEC_NEWCYCLE
+                               `INSN_cc_Z:     if (~`_F[7]) `EXEC_NEWCYCLE
+                               `INSN_cc_NC:    if (`_F[4])  `EXEC_NEWCYCLE
+                               `INSN_cc_C:     if (~`_F[4]) `EXEC_NEWCYCLE

                                endcase
                                `EXEC_READ(`_SP)        // retry the read
                        end
                                endcase
                                `EXEC_READ(`_SP)        // retry the read
                        end