Add a first cut at strataflash support

diff --git a/CoreTop.ucf b/CoreTop.ucf
index 55b46529613be37c8d61fe04b0e9d4da6d3d504a..5e374104b662cbcb2bbb10d81b8d3903b06cf629 100644 (file)
--- a/CoreTop.ucf
+++ b/CoreTop.ucf
@@ -103,5 +103,8 @@ NET "cr_A<20>" LOC="K3" | SLEW="fast";
 NET "cr_A<21>" LOC="D1" | SLEW="fast";
 NET "cr_A<22>" LOC="K6" | SLEW="fast";
 
 NET "cr_A<21>" LOC="D1" | SLEW="fast";
 NET "cr_A<22>" LOC="K6" | SLEW="fast";
 

+NET "st_nCE" LOC="R5" | SLEW="fast";
+NET "st_nRST" LOC="T5" | SLEW="fast";
+

 NET "ps2c" LOC="R12" | CLOCK_DEDICATED_ROUTE = FALSE;
 NET "ps2c" LOC="R12" | CLOCK_DEDICATED_ROUTE = FALSE;

-NET "ps2d" LOC="P11";
\ No newline at end of file
+NET "ps2d" LOC="P11";

diff --git a/System.v b/System.v
index 02b424cf54b03a366359019648aff429c90243e7..e0baebe3c65f9dad345554cc8137b35010ed4282 100644 (file)
--- a/System.v
+++ b/System.v
@@ -81,6 +81,7 @@ module CellularRAM(
        inout [7:0] data,
        input wr, rd,
        output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
        inout [7:0] data,
        input wr, rd,
        output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,

+       output wire st_nCE, st_nRST,

        output wire [22:0] cr_A,
        inout [15:0] cr_DQ);
        
        output wire [22:0] cr_A,
        inout [15:0] cr_DQ);
        


@@ -88,6 +89,7 @@ module CellularRAM(
        parameter ADDR_PROGADDRM = 16'hFF61;
        parameter ADDR_PROGADDRL = 16'hFF62;
        parameter ADDR_PROGDATA = 16'hFF63;
        parameter ADDR_PROGADDRM = 16'hFF61;
        parameter ADDR_PROGADDRL = 16'hFF62;
        parameter ADDR_PROGDATA = 16'hFF63;

+       parameter ADDR_PROGFLASH = 16'hFF65;

        parameter ADDR_MBC = 16'hFF64;
        
        reg rdlatch = 0, wrlatch = 0;
        parameter ADDR_MBC = 16'hFF64;
        
        reg rdlatch = 0, wrlatch = 0;


@@ -102,25 +104,28 @@ module CellularRAM(
                                                // low 7 bits are the MBC that we are emulating
        
        assign cr_nADV = 0;     /* Addresses are always valid! :D */
                                                // low 7 bits are the MBC that we are emulating
        
        assign cr_nADV = 0;     /* Addresses are always valid! :D */

-       assign cr_nCE = 0;      /* The chip is enabled */
+       assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */

        assign cr_nLB = 0;      /* Lower byte is enabled */
        assign cr_nUB = 0;      /* Upper byte is enabled */
        assign cr_CRE = 0;      /* Data writes, not config */
        assign cr_CLK = 0;      /* Clock? I think not! */
        
        assign cr_nLB = 0;      /* Lower byte is enabled */
        assign cr_nUB = 0;      /* Upper byte is enabled */
        assign cr_CRE = 0;      /* Data writes, not config */
        assign cr_CLK = 0;      /* Clock? I think not! */
        

-       wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
+       assign st_nRST = 1;     /* Keep the strataflash out of reset. */
+       assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
+       
+       wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);

        
        reg [3:0] rambank = 0;
        reg [8:0] rombank = 1;
        
        assign cr_nOE = decode ? ~rdlatch : 1;
        
        reg [3:0] rambank = 0;
        reg [8:0] rombank = 1;
        
        assign cr_nOE = decode ? ~rdlatch : 1;

-       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
+       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;

        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
        assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
                        (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
                        (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
        assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
                        (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
                        (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :

-                       (addrlatch == ADDR_PROGDATA) ? progaddr :
+                       ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :

                        23'b0;
        
        always @(posedge clk) begin
                        23'b0;
        
        always @(posedge clk) begin


@@ -229,7 +234,7 @@ module CoreTop(
        input serin,
        output wire [3:0] digits,
        output wire [7:0] seven,
        input serin,
        output wire [3:0] digits,
        output wire [7:0] seven,

-       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,

        output wire [22:0] cr_A,
        inout [15:0] cr_DQ,
        input ps2c, ps2d,
        output wire [22:0] cr_A,
        inout [15:0] cr_DQ,
        input ps2c, ps2d,


@@ -314,7 +319,9 @@ module CoreTop(
                .cr_nUB(cr_nUB),
                .cr_CLK(cr_CLK),
                .cr_A(cr_A),
                .cr_nUB(cr_nUB),
                .cr_CLK(cr_CLK),
                .cr_A(cr_A),

-               .cr_DQ(cr_DQ));
+               .cr_DQ(cr_DQ),
+               .st_nCE(st_nCE),
+               .st_nRST(st_nRST));

 `endif
        
        wire lcdhs, lcdvs, lcdclk;
 `endif
        
        wire lcdhs, lcdvs, lcdclk;