Make it synthesizable.

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 7770eb008676e674792cd2feea4e53b9fad09ccc..b522e2c3cb07048d94fca2c409c934d11d90a75a 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index cb80cb8fcfe008cd0a85c16dc8e9a796fc1acc13..968cd2662920cd99f901106a3836ed3336c29298 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -70,18 +70,18 @@ module GBZ80Core(
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        initial begin
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        initial begin

-               registers[ 0] = 0;
-               registers[ 1] = 0;
-               registers[ 2] = 0;
-               registers[ 3] = 0;
-               registers[ 4] = 0;
-               registers[ 5] = 0;
-               registers[ 6] = 0;
-               registers[ 7] = 0;
-               registers[ 8] = 0;
-               registers[ 9] = 0;
-               registers[10] = 0;
-               registers[11] = 0;
+               registers[ 0] <= 0;
+               registers[ 1] <= 0;
+               registers[ 2] <= 0;
+               registers[ 3] <= 0;
+               registers[ 4] <= 0;
+               registers[ 5] <= 0;
+               registers[ 6] <= 0;
+               registers[ 7] <= 0;
+               registers[ 8] <= 0;
+               registers[ 9] <= 0;
+               registers[10] <= 0;
+               registers[11] <= 0;

        end
 
        always @(posedge clk)
        end
 
        always @(posedge clk)


@@ -364,12 +364,12 @@ module GBZ80Core(
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
                                0: begin
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
                                0: begin

-                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=

                                                        {registers[`REG_SPH],registers[`REG_SPL]} - 1;
                                                cycle <= 1;
                                        end
                                1:      begin
                                                        {registers[`REG_SPH],registers[`REG_SPL]} - 1;
                                                cycle <= 1;
                                        end
                                1:      begin

-                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=

                                                        {registers[`REG_SPH],registers[`REG_SPL]} - 1;
                                                cycle <= 2;
                                        end
                                                        {registers[`REG_SPH],registers[`REG_SPL]} - 1;
                                                cycle <= 2;
                                        end


@@ -381,7 +381,7 @@ module GBZ80Core(
                                case (cycle)
                                0:      begin
                                                cycle <= 1;
                                case (cycle)
                                0:      begin
                                                cycle <= 1;

-                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=

                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                1:      begin
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                1:      begin


@@ -391,7 +391,7 @@ module GBZ80Core(
                                                `INSN_stack_DE: registers[`REG_E] <= rdata;
                                                `INSN_stack_HL: registers[`REG_L] <= rdata;
                                                endcase
                                                `INSN_stack_DE: registers[`REG_E] <= rdata;
                                                `INSN_stack_HL: registers[`REG_L] <= rdata;
                                                endcase

-                                               {registers[`REG_SPH],registers[`REG_SPL]} =
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=

                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                                cycle <= 2;
                                        end
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                                cycle <= 2;
                                        end