`define INSN_BIT 9'b101xxxxxx
`define INSN_RES 9'b110xxxxxx
`define INSN_SET 9'b111xxxxxx
+`define INSN_ADD_HL 9'b000xx1001
`define INSN_cc_NZ 2'b00
`define INSN_cc_Z 2'b01
CPUDCM.v insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
insn_ldm8_a.v insn_ldm16_a.v insn_ldbcde_a.v insn_alu_ext.v \
- insn_bit.v insn_two_byte.v insn_incdec_reg8.v
+ insn_bit.v insn_two_byte.v insn_incdec_reg8.v insn_add_hl.v
all: CoreTop.svf
`include "insn_two_byte.v"
`include "insn_bit.v"
`include "insn_alu_ext.v"
+`include "insn_add_hl.v"
--- /dev/null
+`ifdef EXECUTE
+ `INSN_ADD_HL: begin
+ case (cycle)
+ 0: case (opcode[5:4])
+ `INSN_reg16_BC: {tmp,tmp2} <= `_BC;
+ `INSN_reg16_DE: {tmp,tmp2} <= `_DE;
+ `INSN_reg16_HL: {tmp,tmp2} <= `_HL;
+ `INSN_reg16_SP: {tmp,tmp2} <= `_SP;
+ endcase
+ 1: begin
+ `EXEC_INC_PC
+ `EXEC_NEWCYCLE
+ end
+ endcase
+ end
+`endif
+
+`ifdef WRITEBACK
+ `INSN_ADD_HL: begin
+ case (cycle)
+ 0: {tmp,tmp2} <= `_HL + {tmp,tmp2};
+ 1: begin
+ `_F <= { /* Z */ `_F[7],
+ /* N */ 1'b0,
+ /* H */ (({`_HL} + {tmp,tmp2}) & 16'h1000) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,`_HL} + {1'b0,tmp,tmp2}) >> 16 == 1) ? 1'b1 : 1'b0,
+ `_F[3:0]
+ };
+ `_HL <= {tmp, tmp2};
+ end
+ endcase
+ end
+`endif
bits insn notes
0000 1000 LD 16m16,SP loads SP
-0000 1001 ADD HL, BC
0001 0000 STOP
-0001 1001 ADD HL, DE
-0010 1001 ADD HL, HL
-0011 1001 ADD HL, SP
0111 0110 HALT Danger! Helvetica!
1100 1011 - - - see two-byte opcodes below
1110 1000 ADD SP, imm8