Add an interrupt ack, so that interrupts are cleared automatically. This fixes APOCAL...
[fpgaboy.git] / GBZ80Core.v
1 `define REG_A   0
2 `define REG_B   1
3 `define REG_C   2
4 `define REG_D   3
5 `define REG_E   4
6 `define REG_F   5
7 `define REG_H   6
8 `define REG_L   7
9 `define REG_SPH 8
10 `define REG_SPL 9
11 `define REG_PCH 10
12 `define REG_PCL 11
13
14 `define _A      registers[`REG_A]
15 `define _B      registers[`REG_B]
16 `define _C      registers[`REG_C]
17 `define _D      registers[`REG_D]
18 `define _E      registers[`REG_E]
19 `define _F      registers[`REG_F]
20 `define _H      registers[`REG_H]
21 `define _L      registers[`REG_L]
22 `define _SPH    registers[`REG_SPH]
23 `define _SPL    registers[`REG_SPL]
24 `define _PCH    registers[`REG_PCH]
25 `define _PCL    registers[`REG_PCL]
26 `define _AF     {`_A, `_F}
27 `define _BC     {`_B, `_C}
28 `define _DE     {`_D, `_E}
29 `define _HL     {`_H, `_L}
30 `define _SP     {`_SPH, `_SPL}
31 `define _PC     {`_PCH, `_PCL}
32
33 `define FLAG_Z  8'b10000000
34 `define FLAG_N  8'b01000000
35 `define FLAG_H  8'b00100000
36 `define FLAG_C  8'b00010000
37
38 `define STATE_FETCH             2'h0
39 `define STATE_DECODE            2'h1
40 `define STATE_EXECUTE           2'h2
41 `define STATE_WRITEBACK         2'h3
42
43 `define INSN_LD_reg_imm8        9'b000xxx110
44 `define INSN_HALT               9'b001110110
45 `define INSN_LD_HL_reg          9'b001110xxx
46 `define INSN_LD_reg_HL          9'b001xxx110
47 `define INSN_LD_reg_reg         9'b001xxxxxx
48 `define INSN_LD_reg_imm16       9'b000xx0001
49 `define INSN_LD_SP_HL           9'b011111001
50 `define INSN_PUSH_reg           9'b011xx0101
51 `define INSN_POP_reg            9'b011xx0001
52 `define INSN_LDH_AC             9'b0111x0010    // Either LDH A,(C) or LDH (C),A
53 `define INSN_LDx_AHL            9'b0001xx010    // LDD/LDI A,(HL) / (HL),A
54 `define INSN_ALU8               9'b010xxxxxx    // 10 xxx yyy
55 `define INSN_ALU8IMM            9'b011xxx110
56 `define INSN_NOP                9'b000000000
57 `define INSN_RST                9'b011xxx111
58 `define INSN_RET                9'b0110x1001    // 1 = RETI, 0 = RET
59 `define INSN_RETCC              9'b0110xx000
60 `define INSN_CALL               9'b011001101
61 `define INSN_CALLCC             9'b0110xx100    // Not that call/cc.
62 `define INSN_JP_imm             9'b011000011
63 `define INSN_JPCC_imm           9'b0110xx010
64 `define INSN_ALU_A              9'b000xxx111
65 `define INSN_JP_HL              9'b011101001
66 `define INSN_JR_imm             9'b000011000
67 `define INSN_JRCC_imm           9'b0001xx000
68 `define INSN_INCDEC16           9'b000xxx011
69 `define INSN_VOP_INTR           9'b011111100    // 0xFC is grabbed by the fetch if there is an interrupt pending.
70 `define INSN_DI                 9'b011110011
71 `define INSN_EI                 9'b011111011
72 `define INSN_INCDEC_HL          9'b00011010x
73 `define INSN_INCDEC_reg8        9'b000xxx10x
74 `define INSN_LD8M_A             9'b0111x0000    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
75 `define INSN_LD16M_A            9'b0111x1010    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
76 `define INSN_LDBCDE_A           9'b0000xx010
77 `define INSN_TWO_BYTE           9'b011001011    // prefix for two-byte opqodes
78 `define INSN_ALU_EXT            9'b100xxxxxx
79 `define INSN_BIT                9'b101xxxxxx
80 `define INSN_RES                9'b110xxxxxx
81 `define INSN_SET                9'b111xxxxxx
82
83 `define INSN_cc_NZ              2'b00
84 `define INSN_cc_Z               2'b01
85 `define INSN_cc_NC              2'b10
86 `define INSN_cc_C               2'b11
87
88 `define INSN_reg_A              3'b111
89 `define INSN_reg_B              3'b000
90 `define INSN_reg_C              3'b001
91 `define INSN_reg_D              3'b010
92 `define INSN_reg_E              3'b011
93 `define INSN_reg_H              3'b100
94 `define INSN_reg_L              3'b101
95 `define INSN_reg_dHL            3'b110
96 `define INSN_reg16_BC           2'b00
97 `define INSN_reg16_DE           2'b01
98 `define INSN_reg16_HL           2'b10
99 `define INSN_reg16_SP           2'b11
100 `define INSN_stack_AF           2'b11
101 `define INSN_stack_BC           2'b00
102 `define INSN_stack_DE           2'b01
103 `define INSN_stack_HL           2'b10
104 `define INSN_alu_ADD            3'b000
105 `define INSN_alu_ADC            3'b001
106 `define INSN_alu_SUB            3'b010
107 `define INSN_alu_SBC            3'b011
108 `define INSN_alu_AND            3'b100
109 `define INSN_alu_XOR            3'b101
110 `define INSN_alu_OR             3'b110
111 `define INSN_alu_CP             3'b111          // Oh lawd, is dat some CP?
112 `define INSN_alu_RLCA           3'b000
113 `define INSN_alu_RRCA           3'b001
114 `define INSN_alu_RLA            3'b010
115 `define INSN_alu_RRA            3'b011
116 `define INSN_alu_DAA            3'b100
117 `define INSN_alu_CPL            3'b101
118 `define INSN_alu_SCF            3'b110
119 `define INSN_alu_CCF            3'b111
120 `define INSN_alu_RLC            3'b000
121 `define INSN_alu_RRC            3'b001
122 `define INSN_alu_RL             3'b010
123 `define INSN_alu_RR             3'b011
124 `define INSN_alu_DA_SLA         3'b100
125 `define INSN_alu_CPL_SRA        3'b101
126 `define INSN_alu_SCF_SWAP       3'b110
127 `define INSN_alu_CCF_SRL        3'b111
128
129 `define EXEC_INC_PC             `_PC <= `_PC + 1;
130 `define EXEC_NEXTADDR_PCINC     address <= `_PC + 1;
131 `define EXEC_NEWCYCLE           begin newcycle <= 1; rd <= 1; wr <= 0; end
132 `define EXEC_NEWCYCLE_TWOBYTE   begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
133 `ifdef verilator
134         `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
135         `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
136 `else
137         `ifdef isim
138                 `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
139                 `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
140         `else
141 /* Work around XST's retarded bugs :\ */
142                 `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
143                 `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
144         `endif
145 `endif
146
147 module GBZ80Core(
148         input clk,
149         inout [15:0] bus0address,       /* BUS_* is latched on STATE_FETCH. */
150         inout [7:0] bus0data,
151         inout bus0wr, bus0rd,
152         inout [15:0] bus1address,       /* BUS_* is latched on STATE_FETCH. */
153         inout [7:0] bus1data,
154         inout bus1wr, bus1rd,
155         input irq, output reg irqack, input [7:0] jaddr,
156         output reg [1:0] state);
157
158 //      reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
159         reg [2:0] cycle;                                        /* Cycle for instructions. */
160         
161         reg [7:0] registers[11:0];
162         
163         reg [15:0] address;                             /* Address for the next bus operation. */
164         
165         reg [8:0] opcode;                               /* Opcode from the current machine cycle. */
166
167         reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
168         reg rd, wr, newcycle, twobyte;
169         
170         reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
171         
172         reg [7:0] buswdata;
173         wire [7:0] busdata;
174         
175         reg [15:0] busaddress;
176         reg buswr, busrd;
177         
178         reg bootstrap_enb;
179         
180         wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF))   /* 0 or 1 depending on which bus */
181                 `ifdef isim
182                         || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
183                 `endif
184                         ;
185                 
186         assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
187         assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
188         assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
189         assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
190         assign busdata = (bus == 0) ? bus0data : bus1data;
191         assign bus0rd = (bus == 0) ? busrd : 1'b0;
192         assign bus1rd = (bus == 1) ? busrd : 1'b0;
193         assign bus0wr = (bus == 0) ? buswr : 1'b0;
194         assign bus1wr = (bus == 1) ? buswr : 1'b0;
195
196         reg ie, iedelay;
197
198         wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
199         wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
200         wire [7:0] alu_res;
201         wire [3:0] f_res;
202
203         assign rlc   = {tmp[6:0],tmp[7]};
204         assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
205                         ,2'b0,
206                         tmp[7]};
207
208         assign rrc   = {tmp[0],tmp[7:1]};
209         assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
210                         2'b0,
211                         tmp[0]};
212
213         assign rl    = {tmp[6:0],`_F[4]};
214         assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
215                         2'b0,
216                         tmp[7]};
217
218         assign rr    = {`_F[4],tmp[7:1]};
219         assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
220                         2'b0,
221                         tmp[0]};
222
223         assign sla   = {tmp[6:0],1'b0};
224         assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
225                         2'b0,
226                         tmp[7]};
227
228         assign sra   = {tmp[7],tmp[7:1]};
229 //      assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
230
231         assign swap  = {tmp[3:0],tmp[7:4]};
232         assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
233                         3'b0};
234
235         assign srl   = {1'b0,tmp[7:1]};
236         assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
237                         2'b0,
238                         tmp[0]};
239         assign sraf  = srlf;
240
241         /*  Y U Q  */
242         assign {alu_res,f_res} =
243                 opcode[5] ? (
244                         opcode[4] ? (
245                                 opcode[3] ? {srl,srlf} : {swap,swapf}
246                         ) : (
247                                 opcode[3] ? {sra,sraf} : {sla,slaf}
248                         )
249                 ) : (
250                         opcode[4] ? (
251                                 opcode[3] ? {rr,rrf} : {rl,rlf}
252                         ) : (
253                                 opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
254                         )
255                 );
256
257         initial begin
258                 `_A <= 0;
259                 `_B <= 0;
260                 `_C <= 0;
261                 `_D <= 0;
262                 `_E <= 0;
263                 `_F <= 0;
264                 `_H <= 0;
265                 `_L <= 0;
266                 `_PCH <= 0;
267                 `_PCL <= 0;
268                 `_SPH <= 0;
269                 `_SPL <= 0;
270                 rd <= 1;
271                 wr <= 0;
272                 newcycle <= 1;
273                 state <= 0;
274                 cycle <= 0;
275                 busrd <= 0;
276                 buswr <= 0;
277                 busaddress <= 0;
278                 ie <= 0;
279                 iedelay <= 0;
280                 opcode <= 0;
281                 state <= `STATE_WRITEBACK;
282                 cycle <= 0;
283                 twobyte <= 0;
284                 bootstrap_enb <= 1;
285                 irqack <= 0;
286         end
287
288         always @(negedge clk)   /* Set things up at the negedge to prepare for the posedge. */
289                 case (state)
290                 `STATE_FETCH: begin
291                         if (newcycle) begin
292                                 busaddress <= `_PC;
293                                 buswr <= 0;
294                                 busrd <= 1;
295                         end else begin
296                                 busaddress <= address;
297                                 buswr <= wr;
298                                 busrd <= rd;
299                                 if (wr) begin
300                                         buswdata <= wdata;
301                                         if (address == 16'hFF50)
302                                                 bootstrap_enb <= 0;
303                                 end
304                         end
305                 end
306                 `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
307                         buswr <= 0;
308                         busrd <= 0;
309                 end
310                 endcase
311         
312         always @(posedge clk)
313                 case (state)
314                 `STATE_FETCH: begin
315                         /* Things are set up in negedge so that something looking on posedge will get his shit. */
316                         state <= `STATE_DECODE;
317                 end
318                 `STATE_DECODE: begin
319                         if (newcycle) begin
320                                 if (twobyte) begin
321                                         opcode <= {1'b1,busdata};
322                                         twobyte <= 0;
323                                 end else if (ie && irq)
324                                         opcode <= `INSN_VOP_INTR;
325                                 else
326                                         opcode <= {1'b0,busdata};
327                                 newcycle <= 0;
328                                 rdata <= busdata;
329                                 cycle <= 0;
330                         end else begin
331                                 if (rd) rdata <= busdata;       /* Still valid because peripherals are now expected to keep it held valid. */
332                                 cycle <= cycle + 1;
333                         end
334                         if (iedelay) begin
335                                 ie <= 1;
336                                 iedelay <= 0;
337                         end
338                         wr <= 0;
339                         rd <= 0;
340                         address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
341                         wdata <= 8'bxxxxxxxx;
342                         state <= `STATE_EXECUTE;
343                 end
344                 `STATE_EXECUTE: begin
345                 `ifdef isim
346                         if (opcode[7:0] === 8'bxxxxxxxx)
347                                 $stop;
348                 `endif
349                         casex (opcode)
350                         `define EXECUTE
351                         `include "allinsns.v"
352                         `undef EXECUTE
353                         default:
354                                 $stop;
355                         endcase
356                         state <= `STATE_WRITEBACK;
357                 end
358                 `STATE_WRITEBACK: begin
359                         casex (opcode)
360                         `define WRITEBACK
361                         `include "allinsns.v"
362                         `undef WRITEBACK
363                         default:
364                                 $stop;
365                         endcase
366                         state <= `STATE_FETCH;
367                 end
368                 endcase
369 endmodule
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