Some reworks to prepare for transition to makefile. Stack bugfixes.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 57c22d20e27188d7f633bb66a1f74189ca8ebfbd..ae6ff0076d3676591d162f1b6a1eb5b903b83087 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -95,8 +95,8 @@ module GBZ80Core(
        output reg buswr = 0, output reg busrd = 0,
        input irq, input [7:0] jaddr);
        
-       reg [1:0] state = 0;                                    /* State within this bus cycle (see STATE_*). */
-       reg [2:0] cycle = 0;                                    /* Cycle for instructions. */
+       reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
+       reg [2:0] cycle;                                        /* Cycle for instructions. */
        
        reg [7:0] registers[11:0];
        
@@ -105,7 +105,7 @@ module GBZ80Core(
        reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
        
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
-       reg rd = 1, wr = 0, newcycle = 1;
+       reg rd, wr, newcycle;
        
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
@@ -127,7 +127,6 @@ module GBZ80Core(
                registers[ 9] <= 0;
                registers[10] <= 0;
                registers[11] <= 0;
-               ie <= 0;
                rd <= 1;
                wr <= 0;
                newcycle <= 1;
@@ -136,7 +135,11 @@ module GBZ80Core(
                busrd <= 0;
                buswr <= 0;
                busaddress <= 0;
+               ie <= 0;
                iedelay <= 0;
+               opcode <= 0;
+               state <= `STATE_WRITEBACK;
+               cycle <= 0;
        end
 
        always @(posedge clk)
@@ -302,7 +305,7 @@ module GBZ80Core(
                                        end
                                1:      begin
                                                wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                                case (opcode[5:4])
                                                `INSN_stack_AF: wdata <= registers[`REG_F];
                                                `INSN_stack_BC: wdata <= registers[`REG_C];
@@ -325,7 +328,7 @@ module GBZ80Core(
                                        end
                                1:      begin
                                                rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                2:      begin
                                                `EXEC_NEWCYCLE;
@@ -677,18 +680,16 @@ module GBZ80Core(
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
-                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                               1:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                               0:      begin /* type F */ end
+                               1:      begin /* type F */ end
                                2:      begin /* type F */ end
-                               3:      begin /* type F */ end
+                               3:      {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                               {registers[`REG_SPH],registers[`REG_SPL]} - 2;
                                endcase
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)
-                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                               0:      begin end
                                1:      begin
                                                case (opcode[5:4])
                                                `INSN_stack_AF: registers[`REG_F] <= rdata;
@@ -696,8 +697,6 @@ module GBZ80Core(
                                                `INSN_stack_DE: registers[`REG_E] <= rdata;
                                                `INSN_stack_HL: registers[`REG_L] <= rdata;
                                                endcase
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                2:      begin
                                                case (opcode[5:4])
@@ -706,6 +705,8 @@ module GBZ80Core(
                                                `INSN_stack_DE: registers[`REG_D] <= rdata;
                                                `INSN_stack_HL: registers[`REG_H] <= rdata;
                                                endcase
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
                                        end
                                endcase
                        end
@@ -939,12 +940,13 @@ module GBZ80Core(
                        `INSN_VOP_INTR: begin
                                case (cycle)
                                0:      begin end
-                               1:      {registers[`REG_SPH],registers[`REG_SPL]}
-                                               <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                               1:      begin end
                                2:      begin
                                                ie <= 0;
                                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                                        {8'b0,jaddr};
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
                                        end
                                endcase
                        end