New generation makefile. Code that will reliably break the machine.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 7319ebf6aceb8cc2f7b7f72a3f0877bb93a39aaa..0afc09066159f17645bd92537eab33fc43f5f908 100644 (file)
--- a/System.v
+++ b/System.v
@@ -26,7 +26,6 @@ module InternalRAM(
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
-       wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
@@ -46,7 +45,7 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
@@ -97,12 +96,11 @@ module CoreTop(
                .rd(rd));
        
        AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-        .freeze(buttons[0])
-    );
+               .addr(addr), 
+               .clk(clk), 
+               .digit(digits), 
+               .out(seven),
+               .freeze(buttons[0]));
         
        Switches sw(
                .address(addr),
@@ -115,20 +113,21 @@ module CoreTop(
                );
 
        UART nouart (   /* no u */
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+               .clk(clk), 
+               .wr(wr), 
+               .rd(rd), 
+               .addr(addr), 
+               .data(data), 
+               .serial(serio)
+               );
 
-  InternalRAM ram(
+       InternalRAM ram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
-               .rd(rd));
+               .rd(rd)
+               );
 
        Timer tmr(
                .clk(clk),
@@ -136,7 +135,8 @@ module CoreTop(
                .rd(rd),
                .addr(addr),
                .data(data),
-               .irq(tmrirq));
+               .irq(tmrirq)
+               );
        
        Interrupt intr(
                .clk(clk),
@@ -162,8 +162,8 @@ module TestBench();
        wire irq, tmrirq;
        wire [7:0] jaddr;
        
-//     wire [7:0] leds;
-//     wire [7:0] switches;
+       wire [7:0] leds;
+       wire [7:0] switches;
        
        always #10 clk <= ~clk;
        GBZ80Core core(
@@ -220,12 +220,12 @@ module TestBench();
                .master(irq),
                .jaddr(jaddr));
        
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+       Switches sw(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd),
+               .switches(switches),
+               .ledout(leds));
 endmodule