`define INSN_JP_HL 8'b11101001
`define INSN_JR_imm 8'b00011000
`define INSN_JRCC_imm 8'b001xx000
+`define INSN_INCDEC16 8'b00xxx011
+`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI 8'b11110011
+`define INSN_EI 8'b11111011
`define INSN_cc_NZ 2'b00
`define INSN_cc_Z 2'b01
module GBZ80Core(
input clk,
- output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
+ output reg [15:0] busaddress = 0, /* BUS_* is latched on STATE_FETCH. */
inout [7:0] busdata,
- output reg buswr, output reg busrd);
+ output reg buswr = 0, output reg busrd = 0,
+ input irq, input [7:0] jaddr);
- reg [1:0] state = 0; /* State within this bus cycle (see STATE_*). */
- reg [2:0] cycle = 0; /* Cycle for instructions. */
+ reg [1:0] state; /* State within this bus cycle (see STATE_*). */
+ reg [2:0] cycle; /* Cycle for instructions. */
reg [7:0] registers[11:0];
reg [7:0] opcode; /* Opcode from the current machine cycle. */
reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
- reg rd = 1, wr = 0, newcycle = 1;
+ reg rd, wr, newcycle;
reg [7:0] tmp, tmp2; /* Generic temporary regs. */
reg [7:0] buswdata;
assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
- reg ie = 0;
+ reg ie = 0, iedelay = 0;
initial begin
registers[ 0] <= 0;
registers[ 9] <= 0;
registers[10] <= 0;
registers[11] <= 0;
- ie <= 0;
rd <= 1;
wr <= 0;
newcycle <= 1;
state <= 0;
cycle <= 0;
+ busrd <= 0;
+ buswr <= 0;
+ busaddress <= 0;
+ ie <= 0;
+ iedelay <= 0;
+ opcode <= 0;
+ state <= `STATE_WRITEBACK;
+ cycle <= 0;
end
always @(posedge clk)
end
`STATE_DECODE: begin
if (newcycle) begin
- opcode <= busdata;
+ if (ie && irq)
+ opcode <= `INSN_VOP_INTR;
+ else
+ opcode <= busdata;
rdata <= busdata;
newcycle <= 0;
cycle <= 0;
if (rd) rdata <= busdata;
cycle <= cycle + 1;
end
+ if (iedelay) begin
+ ie <= 1;
+ iedelay <= 0;
+ end
buswr <= 0;
busrd <= 0;
wr <= 0;
end
1: begin
wr <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
case (opcode[5:4])
`INSN_stack_AF: wdata <= registers[`REG_F];
`INSN_stack_BC: wdata <= registers[`REG_C];
end
1: begin
rd <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]};
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
end
2: begin
`EXEC_NEWCYCLE;
address <= {registers[`REG_SPH],registers[`REG_SPL]};
end
1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret!
- `EXEC_INC_PC;
- case (opcode[4:3]) // cycle 1 is skipped if we are not retcc
+ `EXEC_INC_PC; // cycle 1 is skipped if we are not retcc
+ case (opcode[4:3])
`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
`INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
end
endcase
end
+ `INSN_INCDEC16: begin
+ case (cycle)
+ 0: begin
+ case (opcode[5:4])
+ `INSN_reg16_BC: begin
+ tmp <= registers[`REG_B];
+ tmp2 <= registers[`REG_C];
+ end
+ `INSN_reg16_DE: begin
+ tmp <= registers[`REG_D];
+ tmp2 <= registers[`REG_E];
+ end
+ `INSN_reg16_HL: begin
+ tmp <= registers[`REG_H];
+ tmp2 <= registers[`REG_L];
+ end
+ `INSN_reg16_SP: begin
+ tmp <= registers[`REG_SPH];
+ tmp2 <= registers[`REG_SPL];
+ end
+ endcase
+ end
+ 1: begin
+ `EXEC_INC_PC;
+ `EXEC_NEWCYCLE;
+ end
+ endcase
+ end
+ `INSN_VOP_INTR: begin
+ case (cycle)
+ 0: begin
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ wdata <= registers[`REG_PCH];
+ wr <= 1;
+ end
+ 1: begin
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ wdata <= registers[`REG_PCL];
+ wr <= 1;
+ end
+ 2: begin
+ `EXEC_NEWCYCLE;
+ end
+ endcase
+ end
+ `INSN_DI: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ `INSN_EI: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
default:
$stop;
endcase
end
`INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
case (cycle)
- 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- 1: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ 0: begin /* type F */ end
+ 1: begin /* type F */ end
2: begin /* type F */ end
- 3: begin /* type F */ end
+ 3: {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 2;
endcase
end
`INSN_POP_reg: begin /* POP is 12 cycles! */
case (cycle)
- 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+ 0: begin end
1: begin
case (opcode[5:4])
`INSN_stack_AF: registers[`REG_F] <= rdata;
`INSN_stack_DE: registers[`REG_E] <= rdata;
`INSN_stack_HL: registers[`REG_L] <= rdata;
endcase
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
end
2: begin
case (opcode[5:4])
`INSN_stack_DE: registers[`REG_D] <= rdata;
`INSN_stack_HL: registers[`REG_H] <= rdata;
endcase
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} + 2;
end
endcase
end
4: begin
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} + 2;
- if (opcode[4] && (opcode != `INSN_RETCC)) /* RETI */
+ if (opcode[4] && opcode[0]) /* RETI */
ie <= 1;
end
endcase
{tmp[7]?8'hFF:8'h00,tmp};
endcase
end
+ `INSN_INCDEC16: begin
+ case (cycle)
+ 0: {tmp,tmp2} <= {tmp,tmp2} +
+ (opcode[3] ? 16'hFFFF : 16'h0001);
+ 1: begin
+ case (opcode[5:4])
+ `INSN_reg16_BC: begin
+ registers[`REG_B] <= tmp;
+ registers[`REG_C] <= tmp2;
+ end
+ `INSN_reg16_DE: begin
+ registers[`REG_D] <= tmp;
+ registers[`REG_E] <= tmp2;
+ end
+ `INSN_reg16_HL: begin
+ registers[`REG_H] <= tmp;
+ registers[`REG_L] <= tmp2;
+ end
+ `INSN_reg16_SP: begin
+ registers[`REG_SPH] <= tmp;
+ registers[`REG_SPL] <= tmp2;
+ end
+ endcase
+ end
+ endcase
+ end
+ `INSN_VOP_INTR: begin
+ case (cycle)
+ 0: begin end
+ 1: begin end
+ 2: begin
+ ie <= 0;
+ {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {8'b0,jaddr};
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ end
+ endcase
+ end
+ `INSN_DI: ie <= 0;
+ `INSN_EI: iedelay <= 1;
default:
$stop;
endcase
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