Cleanups to make code nicer looking. ALU subtraction fixes.
[fpgaboy.git] / GBZ80Core.v
index e085739..6039b30 100644 (file)
 `define REG_PCH        10
 `define REG_PCL        11
 
+`define _A     registers[`REG_A]
+`define _B     registers[`REG_B]
+`define _C     registers[`REG_C]
+`define _D     registers[`REG_D]
+`define _E     registers[`REG_E]
+`define _F     registers[`REG_F]
+`define _H     registers[`REG_H]
+`define _L     registers[`REG_L]
+`define _SPH   registers[`REG_SPH]
+`define _SPL   registers[`REG_SPL]
+`define _PCH   registers[`REG_PCH]
+`define _PCL   registers[`REG_PCL]
+`define _AF    {`_A, `_F}
+`define _BC    {`_B, `_C}
+`define _DE    {`_D, `_E}
+`define _HL    {`_H, `_L}
+`define _SP    {`_SPH, `_SPL}
+`define _PC    {`_PCH, `_PCL}
+
 `define FLAG_Z 8'b10000000
 `define FLAG_N 8'b01000000
 `define FLAG_H 8'b00100000
 `define INSN_alu_SCF           3'b110
 `define INSN_alu_CCF           3'b111
 
+`define EXEC_INC_PC \
+       `_PC <= `_PC + 1
+`define EXEC_NEXTADDR_PCINC \
+       address <= `_PC + 1
+`define EXEC_NEWCYCLE \
+       begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_WRITE(ad, da) \
+       begin address <= (ad); \
+       wdata <= (da); \
+       wr <= 1; end
+`define EXEC_READ(ad) \
+       begin address <= (ad); \
+       rd <= 1; end
+
 module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
@@ -184,12 +217,7 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
-`define EXEC_INC_PC \
-       {registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEXTADDR_PCINC \
-       address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEWCYCLE \
-       newcycle <= 1; rd <= 1; wr <= 0
+
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"
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