+ `INSN_RST: begin
+ case (cycle)
+ 0: begin
+ wr <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+ wdata <= registers[`REG_PCH];
+ end
+ 1: begin
+ wr <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+ wdata <= registers[`REG_PCL];
+ end
+ 2: begin /* wee */ end
+ 3: begin
+ `EXEC_NEWCYCLE;
+ {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {10'b0,opcode[5:3],3'b0};
+ end
+ endcase
+ end