Start changing things to happen on posedge clock.

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index 1f0ae7d0d31c57fbc648a6aab693e9fbd77fc367..f9d71f4c17ef5bff177a5cd0a7b8dd0e3ce01f09 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -25,7 +25,7 @@ module UART(
        
        assign odata = have_data ? 8'b1 : 8'b0;
 
-       always @ (negedge clk)
+       always @ (posedge clk)
        begin
                /* deal with diqing */
                if(newdata) begin