Start changing things to happen on posedge clock.

[fpgaboy.git] / Timer.v

diff --git a/Timer.v b/Timer.v
index 53f392deae20118ea451112fa123cf2a83391075..e46b38bbaf937d7366c8fdb903ff84a0ce6ddeeb 100644 (file)
--- a/Timer.v
+++ b/Timer.v
@@ -33,7 +33,7 @@ module Timer(
                        (clkdv[7:0] == 8'b0) :
                     0;
 
-       always @ (negedge clk) 
+       always @ (posedge clk) 
        begin
                if(wr) begin
                        case(addr)