Start changing things to happen on posedge clock.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 4c5f85b140bd6291775447bbe18128950e6b7596..8f54685cfd33045ea6ad52b80f155b379a17099e 100644 (file)
--- a/System.v
+++ b/System.v
@@ -41,7 +41,7 @@ module MiniRAM(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
@@ -65,7 +65,7 @@ module InternalRAM(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
@@ -88,7 +88,7 @@ module Switches(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode && rd)
                        odata <= switches;