Start changing things to happen on posedge clock.

[fpgaboy.git] / Sound1.v

diff --git a/Sound1.v b/Sound1.v
index 41abaa539e844f84f72d0cf890a45297b8450a4b..21b1dec2c36ef924c94a7e55ee7a85ebdb1b300e 100644 (file)
--- a/Sound1.v
+++ b/Sound1.v
@@ -34,7 +34,7 @@ module Sound1(
                         addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR10: nr10 <= data;