Start changing things to happen on posedge clock.

[fpgaboy.git] / Interrupt.v

diff --git a/Interrupt.v b/Interrupt.v
index 1450b2cfd0b6ecf8c61e76f7ab8894cc96a3efe4..fcc396b109769355e31e6105eb82cf4b7429ae75 100644 (file)
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -34,7 +34,7 @@ module Interrupt(
                       imasked[3] ? 8'h58 :
                       imasked[4] ? 8'h60 : 8'h00;
 
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
                        case(addr)