Wire switches back up and remove cclk.

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index a036c64e5ad7858422f27515730da6d13c15c9d0..3dd15323fd012ee5d9357038989790776f919bfc 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -9,7 +9,7 @@ module UART(
        input rd,
        input [15:0] addr,
        inout [7:0] data,
-       output reg serial);
+       output reg serial = 1);
        
        wire decode = (addr == `MMAP_ADDR);
        
@@ -19,7 +19,6 @@ module UART(
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
        reg have_data = 0;
-       reg data_end = 0;
        reg [3:0] diqing = 4'b0000;
        
        wire new = (wr) && (!have_data) && decode;