Start changing things to happen on posedge clock.

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 86154433f0322641cfea4e00bbb5cc51e5b3f369..7b402e4fdf7fab3d3f56a0e8e6526085320e38e8 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -78,7 +78,7 @@ module LCDC(
        
        assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
        assign lcdhs = (posx == 2) && rLCDC[7];
-       assign lcdclk = clk4 && rLCDC[7];
+       assign lcdclk = clk4;
        
        wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
        wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
@@ -145,7 +145,8 @@ module LCDC(
        reg [7:0] tileno;
        wire [10:0] tileaddr = {tileno, vypos[2:0]};
        reg [7:0] tilehigh, tilelow;
-       assign pixdata = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);