`define INSN_RST 8'b11xxx111
`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
`define INSN_CALL 8'b11001101
+`define INSN_JP_imm 8'b11000011
+`define INSN_JPCC_imm 8'b110xx010
+`define INSN_ALU_A 8'b00xxx111
+
+`define INSN_cc_NZ 2'b00
+`define INSN_cc_Z 2'b01
+`define INSN_cc_NC 2'b10
+`define INSN_cc_C 2'b11
`define INSN_reg_A 3'b111
`define INSN_reg_B 3'b000
`define INSN_alu_XOR 3'b101
`define INSN_alu_OR 3'b110
`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
+`define INSN_alu_RLCA 3'b000
+`define INSN_alu_RRCA 3'b001
+`define INSN_alu_RLA 3'b010
+`define INSN_alu_RRA 3'b011
+`define INSN_alu_DAA 3'b100
+`define INSN_alu_CPL 3'b101
+`define INSN_alu_SCF 3'b110
+`define INSN_alu_CCF 3'b111
module GBZ80Core(
input clk,
registers[ 9] <= 0;
registers[10] <= 0;
registers[11] <= 0;
+ ie <= 0;
+ rd <= 1;
+ wr <= 0;
+ newcycle <= 1;
+ state <= 0;
+ cycle <= 0;
end
always @(posedge clk)
case (state)
`STATE_FETCH: begin
- if (wr)
- buswdata <= wdata;
- if (newcycle)
+ if (newcycle) begin
busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
- else
+ buswr <= 0;
+ busrd <= 1;
+ end else begin
busaddress <= address;
- buswr <= wr;
- busrd <= rd;
+ buswr <= wr;
+ busrd <= rd;
+ if (wr)
+ buswdata <= wdata;
+ end
state <= `STATE_DECODE;
end
`STATE_DECODE: begin
rdata <= busdata;
newcycle <= 0;
cycle <= 0;
- end else
+ end else begin
if (rd) rdata <= busdata;
+ cycle <= cycle + 1;
+ end
buswr <= 0;
busrd <= 0;
wr <= 0;
endcase
end
end
+ `INSN_ALU_A: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
`INSN_NOP: begin
`EXEC_NEWCYCLE;
`EXEC_INC_PC;
end
endcase
end
+ `INSN_JP_imm,`INSN_JPCC_imm: begin
+ case (cycle)
+ 0: begin
+ `EXEC_INC_PC;
+ `EXEC_NEXTADDR_PCINC;
+ rd <= 1;
+ end
+ 1: begin
+ `EXEC_INC_PC;
+ `EXEC_NEXTADDR_PCINC;
+ rd <= 1;
+ end
+ 2: begin
+ `EXEC_INC_PC;
+ if (!opcode[0]) begin // i.e., JP cc,nn
+ /* We need to check the condition code to bail out. */
+ case (opcode[4:3])
+ `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ endcase
+ end
+ end
+ 3: begin
+ `EXEC_NEWCYCLE;
+ end
+ endcase
+ end
default:
$stop;
endcase
casex (opcode)
`INSN_LD_reg_imm8:
case (cycle)
- 0: cycle <= 1;
+ 0: begin end
1: case (opcode[5:3])
- `INSN_reg_A: begin registers[`REG_A] <= rdata; cycle <= 0; end
- `INSN_reg_B: begin registers[`REG_B] <= rdata; cycle <= 0; end
- `INSN_reg_C: begin registers[`REG_C] <= rdata; cycle <= 0; end
- `INSN_reg_D: begin registers[`REG_D] <= rdata; cycle <= 0; end
- `INSN_reg_E: begin registers[`REG_E] <= rdata; cycle <= 0; end
- `INSN_reg_H: begin registers[`REG_H] <= rdata; cycle <= 0; end
- `INSN_reg_L: begin registers[`REG_L] <= rdata; cycle <= 0; end
- `INSN_reg_dHL: cycle <= 2;
+ `INSN_reg_A: begin registers[`REG_A] <= rdata; end
+ `INSN_reg_B: begin registers[`REG_B] <= rdata; end
+ `INSN_reg_C: begin registers[`REG_C] <= rdata; end
+ `INSN_reg_D: begin registers[`REG_D] <= rdata; end
+ `INSN_reg_E: begin registers[`REG_E] <= rdata; end
+ `INSN_reg_H: begin registers[`REG_H] <= rdata; end
+ `INSN_reg_L: begin registers[`REG_L] <= rdata; end
+ `INSN_reg_dHL: begin /* Go off to cycle 2 */ end
endcase
- 2: cycle <= 0;
+ 2: begin end
endcase
`INSN_HALT: begin
/* Nothing needs happen here. */
/* XXX Interrupts needed for HALT. */
end
`INSN_LD_HL_reg: begin
- case (cycle)
- 0: cycle <= 1;
- 1: cycle <= 0;
- endcase
+ /* Nothing of interest here */
end
`INSN_LD_reg_HL: begin
case (cycle)
- 0: cycle <= 1;
+ 0: begin end
1: begin
case (opcode[5:3])
`INSN_reg_A: registers[`REG_A] <= tmp;
`INSN_reg_H: registers[`REG_H] <= tmp;
`INSN_reg_L: registers[`REG_L] <= tmp;
endcase
- cycle <= 0;
end
endcase
end
end
`INSN_LD_reg_imm16: begin
case (cycle)
- 0: cycle <= 1;
+ 0: begin /* */ end
1: begin
case (opcode[5:4])
`INSN_reg16_BC: registers[`REG_C] <= rdata;
`INSN_reg16_HL: registers[`REG_L] <= rdata;
`INSN_reg16_SP: registers[`REG_SPL] <= rdata;
endcase
- cycle <= 2;
end
2: begin
case (opcode[5:4])
`INSN_reg16_HL: registers[`REG_H] <= rdata;
`INSN_reg16_SP: registers[`REG_SPH] <= rdata;
endcase
- cycle <= 0;
end
endcase
end
`INSN_LD_SP_HL: begin
case (cycle)
- 0: begin
- cycle <= 1;
- registers[`REG_SPH] <= tmp;
- end
- 1: begin
- cycle <= 0;
- registers[`REG_SPL] <= tmp;
- end
+ 0: registers[`REG_SPH] <= tmp;
+ 1: registers[`REG_SPL] <= tmp;
endcase
end
`INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
case (cycle)
- 0: begin
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- cycle <= 1;
- end
- 1: begin
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- cycle <= 2;
- end
- 2: cycle <= 3;
- 3: cycle <= 0;
+ 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ 1: {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ 2: begin /* type F */ end
+ 3: begin /* type F */ end
endcase
end
`INSN_POP_reg: begin /* POP is 12 cycles! */
case (cycle)
- 0: begin
- cycle <= 1;
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
- end
+ 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} + 1;
1: begin
case (opcode[5:4])
`INSN_stack_AF: registers[`REG_F] <= rdata;
endcase
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} + 1;
- cycle <= 2;
end
2: begin
case (opcode[5:4])
`INSN_stack_DE: registers[`REG_D] <= rdata;
`INSN_stack_HL: registers[`REG_H] <= rdata;
endcase
- cycle <= 0;
end
endcase
end
`INSN_LDH_AC: begin
case (cycle)
- 0: cycle <= 1;
- 1: begin
- cycle <= 0;
- if (opcode[4])
- registers[`REG_A] <= rdata;
- end
+ 0: begin /* Type F */ end
+ 1: if (opcode[4])
+ registers[`REG_A] <= rdata;
endcase
end
`INSN_LDx_AHL: begin
case (cycle)
- 0: cycle <= 1;
+ 0: begin /* Type F */ end
1: begin
- cycle <= 0;
if (opcode[3])
registers[`REG_A] <= rdata;
{registers[`REG_H],registers[`REG_L]} <=
`INSN_ALU8: begin
if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
/* Sit on our asses. */
- cycle <= 1;
end else begin /* Actually do the computation! */
case (opcode[5:3])
`INSN_alu_ADD: begin
registers[`REG_F][3:0]
};
end
+ `INSN_alu_SUB: begin
+ registers[`REG_A] <=
+ registers[`REG_A] - tmp;
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b1,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
+ `INSN_alu_SBC: begin
+ registers[`REG_A] <=
+ registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b1,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
`INSN_alu_AND: begin
registers[`REG_A] <=
registers[`REG_A] & tmp;
registers[`REG_F][3:0]
};
end
+ `INSN_alu_CP: begin
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b1,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
default:
$stop;
endcase
end
end
+ `INSN_ALU_A: begin
+ case(opcode[5:3])
+ `INSN_alu_RLCA: begin
+ registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_RRCA: begin
+ registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_RLA: begin
+ registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_RRA: begin
+ registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_CPL: begin
+ registers[`REG_A] <= ~registers[`REG_A];
+ registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
+ end
+ `INSN_alu_SCF: begin
+ registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+ end
+ `INSN_alu_CCF: begin
+ registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
+ end
+ endcase
+ end
`INSN_NOP: begin /* NOP! */ end
`INSN_RST: begin
case (cycle)
- 0: cycle <= 1;
- 1: cycle <= 2;
- 2: cycle <= 3;
- 3: begin
- cycle <= 0;
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]}-2;
- end
+ 0: begin /* type F */ end
+ 1: begin /* type F */ end
+ 2: begin /* type F */ end
+ 3: {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]}-2;
endcase
end
`INSN_RET: begin
case (cycle)
- 0: cycle <= 1;
- 1: begin
- cycle <= 2;
- registers[`REG_PCL] <= rdata;
- end
- 2: begin
- cycle <= 3;
- registers[`REG_PCH] <= rdata;
- end
+ 0: begin /* type F */ end
+ 1: registers[`REG_PCL] <= rdata;
+ 2: registers[`REG_PCH] <= rdata;
3: begin
- cycle <= 0;
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} + 2;
if (opcode[4]) /* RETI */
end
`INSN_CALL: begin
case (cycle)
- 0: cycle <= 1;
- 1: begin
- cycle <= 2;
- tmp <= rdata; // tmp contains newpcl
- end
- 2: begin
- cycle <= 3;
- tmp2 <= rdata; // tmp2 contains newpch
- end
- 3: begin
- cycle <= 4;
- end
- 4: begin
- cycle <= 5;
- registers[`REG_PCH] <= tmp2;
- end
+ 0: begin /* type F */ end
+ 1: tmp <= rdata; // tmp contains newpcl
+ 2: tmp2 <= rdata; // tmp2 contains newpch
+ 3: begin /* type F */ end
+ 4: registers[`REG_PCH] <= tmp2;
5: begin
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} - 2;
registers[`REG_PCL] <= tmp;
- cycle <= 0;
end
endcase
end
+ `INSN_JP_imm,`INSN_JPCC_imm: begin
+ case (cycle)
+ 0: begin /* type F */ end
+ 1: tmp <= rdata; // tmp contains newpcl
+ 2: tmp2 <= rdata; // tmp2 contains newpch
+ 3: {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {tmp2,tmp};
+ endcase
+ end
default:
$stop;
endcase
end
endcase
endmodule
-
-`timescale 1ns / 1ps
-module ROM(
- input [15:0] address,
- inout [7:0] data,
- input clk,
- input wr, rd);
-
- reg [7:0] rom [2047:0];
- initial $readmemh("rom.hex", rom);
-
- wire decode = address[15:13] == 0;
- wire [7:0] odata = rom[address[11:0]];
- assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
- //assign data = rd ? odata : 8'bzzzzzzzz;
-endmodule
-
-module InternalRAM(
- input [15:0] address,
- inout [7:0] data,
- input clk,
- input wr, rd);
-
- reg [7:0] ram [8191:0];
-
- wire decode = (address >= 16'hC000) && (address < 16'hFE00);
- reg [7:0] odata;
- wire idata = data;
- assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-
- always @(negedge clk)
- begin
- if (decode && rd)
- odata <= ram[address[12:0]];
- else if (decode && wr)
- ram[address[12:0]] <= data;
- end
-endmodule
-
-//module Switches(
-// input [15:0] address,
-// inout [7:0] data,
-// input clk,
-// input wr, rd,
-// input [7:0] switches,
-// output reg [7:0] ledout);
-
-// wire decode = address == 16'hFF51;
-// reg [7:0] odata;
-// wire idata = data;
-// assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-
-// always @(negedge clk)
-// begin
-// if (decode && rd)
-// odata <= switches;
-// else if (decode && wr)
-// ledout <= data;
-// end
-//endmodule
-
-module CoreTop(
- input iclk,
- output wire [7:0] leds,
- output serio);
-
- wire clk;
- IBUFG ibuf (.O(clk), .I(iclk));
-
- wire [15:0] addr;
- wire [7:0] data;
- wire wr, rd;
-
- wire [7:0] swleds;
-
- assign leds = clk?{rd,wr,addr[5:0]}:data[7:0];
-
- GBZ80Core core(
- .clk(clk),
- .busaddress(addr),
- .busdata(data),
- .buswr(wr),
- .busrd(rd));
-
- ROM rom(
- .address(addr),
- .data(data),
- .clk(clk),
- .wr(wr),
- .rd(rd));
-
- assign serio = 0;
-endmodule
-
-//module TestBench();
-// reg clk = 0;
-// wire [15:0] addr;
-// wire [7:0] data;
-// wire wr, rd;
-
-// wire [7:0] leds;
-// wire [7:0] switches;
-
-// always #10 clk <= ~clk;
-// GBZ80Core core(
-// .clk(clk),
-// .busaddress(addr),
-// .busdata(data),
-// .buswr(wr),
-// .busrd(rd));
-
-// ROM rom(
-// .clk(clk),
-// .address(addr),
-// .data(data),
-// .wr(wr),
-// .rd(rd));
-
-// InternalRAM ram(
-// .address(addr),
-// .data(data),
-// .clk(clk),
-// .wr(wr),
-// .rd(rd));
-
-// wire serio;
-// UART uart(
-// .addr(addr),
-// .data(data),
-// .clk(clk),
-// .wr(wr),
-// .rd(rd),
-// .serial(serio));
-
-// Switches sw(
-// .clk(clk),
-// .address(addr),
-// .data(data),
-// .wr(wr),
-// .rd(rd),
-// .switches(switches),
-// .leds(leds));
-//endmodule
git.joshuawise.com / fpgaboy.git / blobdiff