Update the 7seg more often.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 0f0496eed4200d7e2f98b8ac9a8ffd3e3952608a..77c3649372a715fc6b5445302332ed3232c66143 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -37,9 +37,13 @@
 `define INSN_RST                               8'b11xxx111
 `define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
 `define INSN_CALL                              8'b11001101
+`define INSN_CALLCC                    8'b110xx100     // Not that call/cc.
 `define INSN_JP_imm                    8'b11000011
 `define INSN_JPCC_imm          8'b110xx010
 `define INSN_ALU_A             8'b00xxx111
+`define INSN_JP_HL                     8'b11101001
+`define INSN_JR_imm                    8'b00011000
+`define INSN_JRCC_imm          8'b001xx000
 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01
@@ -289,7 +293,7 @@ module GBZ80Core(
                                                `INSN_stack_HL: wdata <= registers[`REG_L];
                                                endcase
                                        end
-                               2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+                               2:      begin /* Twiddle thumbs. */ end
                                3:      begin
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
@@ -413,7 +417,7 @@ module GBZ80Core(
                                        end
                                endcase
                        end
-                       `INSN_CALL: begin
+                       `INSN_CALL,`INSN_CALLCC: begin
                                case (cycle)
                                0:      begin
                                                `EXEC_INC_PC;
@@ -427,6 +431,14 @@ module GBZ80Core(
                                        end
                                2:      begin
                                                `EXEC_INC_PC;
+                                               if (!opcode[0]) // i.e., is callcc
+                                                       /* We need to check the condition code to bail out. */
+                                                       case (opcode[4:3])
+                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       endcase
                                        end
                                3:      begin
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
@@ -472,6 +484,33 @@ module GBZ80Core(
                                        end
                                endcase
                        end
+                       `INSN_JP_HL: begin
+                               `EXEC_NEWCYCLE;
+                       end
+                       `INSN_JR_imm,`INSN_JRCC_imm: begin
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               1: begin
+                                               `EXEC_INC_PC;
+                                               if (opcode[5]) begin    // i.e., JP cc,nn
+                                                       /* We need to check the condition code to bail out. */
+                                                       case (opcode[4:3])
+                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       endcase
+                                               end
+                                       end
+                               2:      begin
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase
@@ -752,7 +791,7 @@ module GBZ80Core(
                                        end
                                endcase
                        end
-                       `INSN_CALL: begin
+                       `INSN_CALL,`INSN_CALLCC: begin
                                case (cycle)
                                0:      begin /* type F */ end
                                1:      tmp <= rdata;   // tmp contains newpcl
@@ -775,6 +814,19 @@ module GBZ80Core(
                                                {tmp2,tmp};
                                endcase
                        end
+                       `INSN_JP_HL: begin
+                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                       {registers[`REG_H],registers[`REG_L]};
+                       end
+                       `INSN_JR_imm,`INSN_JRCC_imm: begin
+                               case (cycle)
+                               0:      begin /* type F */ end
+                               1:      tmp <= rdata;
+                               2: {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                               {registers[`REG_PCH],registers[`REG_PCL]} +
+                                               {tmp[7]?8'hFF:8'h00,tmp};
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase