New generation makefile. Code that will reliably break the machine.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 5d4fbedf2acadf14bd48a28dfb153570ed63a1cf..0afc09066159f17645bd92537eab33fc43f5f908 100644 (file)
--- a/System.v
+++ b/System.v
@@ -26,7 +26,6 @@ module InternalRAM(
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
-       wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
@@ -97,12 +96,11 @@ module CoreTop(
                .rd(rd));
        
        AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-        .freeze(buttons[0])
-    );
+               .addr(addr), 
+               .clk(clk), 
+               .digit(digits), 
+               .out(seven),
+               .freeze(buttons[0]));
         
        Switches sw(
                .address(addr),
@@ -115,20 +113,21 @@ module CoreTop(
                );
 
        UART nouart (   /* no u */
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+               .clk(clk), 
+               .wr(wr), 
+               .rd(rd), 
+               .addr(addr), 
+               .data(data), 
+               .serial(serio)
+               );
 
-  InternalRAM ram(
+       InternalRAM ram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
-               .rd(rd));
+               .rd(rd)
+               );
 
        Timer tmr(
                .clk(clk),
@@ -136,7 +135,8 @@ module CoreTop(
                .rd(rd),
                .addr(addr),
                .data(data),
-               .irq(tmrirq));
+               .irq(tmrirq)
+               );
        
        Interrupt intr(
                .clk(clk),