Update the 7seg more often.
[fpgaboy.git] / 7seg.v
diff --git a/7seg.v b/7seg.v
index ed4519a..8e91b03 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -6,7 +6,7 @@ module AddrMon(
        input freeze
        );
 
-       reg [12:0] clkdv;
+       reg [10:0] clkdv;
        reg [1:0] dcount;
        
        reg [15:0] latch = 0;
@@ -24,7 +24,7 @@ module AddrMon(
                        latch <= addr;
        end
 
-       always @ (posedge clkdv[12])
+       always @ (posedge clkdv[10])
        begin
                dcount <= dcount + 1;
 
This page took 0.017667 seconds and 4 git commands to generate.