Add an instruction tester to the test ROM.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 3bc2b16f0e184c9a3e6ff8ea51d8cd82d97fa4b6..e125225ede2924e2c3ce07eb4c2296d4bc0eb454 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -37,6 +37,14 @@
 `define INSN_RST                               8'b11xxx111
 `define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
 `define INSN_CALL                              8'b11001101
 `define INSN_RST                               8'b11xxx111
 `define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
 `define INSN_CALL                              8'b11001101

+`define INSN_JP_imm                    8'b11000011
+`define INSN_JPCC_imm          8'b110xx010
+`define INSN_ALU_A             8'b00xxx111
+
+`define INSN_cc_NZ                     2'b00
+`define INSN_cc_Z                              2'b01
+`define INSN_cc_NC                     2'b10
+`define INSN_cc_C                              2'b11

 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000


@@ -62,6 +70,14 @@
 `define INSN_alu_XOR           3'b101
 `define INSN_alu_OR            3'b110
 `define INSN_alu_CP            3'b111          // Oh lawd, is dat some CP?
 `define INSN_alu_XOR           3'b101
 `define INSN_alu_OR            3'b110
 `define INSN_alu_CP            3'b111          // Oh lawd, is dat some CP?

+`define INSN_alu_RLCA          3'b000
+`define INSN_alu_RRCA          3'b001
+`define INSN_alu_RLA           3'b010
+`define INSN_alu_RRA           3'b011
+`define INSN_alu_DAA           3'b100
+`define INSN_alu_CPL           3'b101
+`define INSN_alu_SCF           3'b110
+`define INSN_alu_CCF           3'b111

 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,


@@ -273,7 +289,7 @@ module GBZ80Core(
                                                `INSN_stack_HL: wdata <= registers[`REG_L];
                                                endcase
                                        end
                                                `INSN_stack_HL: wdata <= registers[`REG_L];
                                                endcase
                                        end

-                               2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+                               2:      begin /* Twiddle thumbs. */ end

                                3:      begin
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                3:      begin
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;


@@ -350,6 +366,10 @@ module GBZ80Core(
                                        endcase
                                end
                        end
                                        endcase
                                end
                        end

+                       `INSN_ALU_A: begin
+                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC;
+                       end

                        `INSN_NOP: begin
                                `EXEC_NEWCYCLE;
                                `EXEC_INC_PC;
                        `INSN_NOP: begin
                                `EXEC_NEWCYCLE;
                                `EXEC_INC_PC;


@@ -423,6 +443,35 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

+                       `INSN_JP_imm,`INSN_JPCC_imm: begin
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               1:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               2:      begin
+                                               `EXEC_INC_PC;
+                                               if (!opcode[0]) begin   // i.e., JP cc,nn
+                                                       /* We need to check the condition code to bail out. */
+                                                       case (opcode[4:3])
+                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       endcase
+                                               end
+                                       end
+                               3:      begin
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -587,6 +636,28 @@ module GBZ80Core(
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
                                                          registers[`REG_F][3:0]
                                                        };
                                        end

+                                       `INSN_alu_SUB: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] - tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b1,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       `INSN_alu_SBC: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b1,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end

                                        `INSN_alu_AND: begin
                                                registers[`REG_A] <=
                                                        registers[`REG_A] & tmp;
                                        `INSN_alu_AND: begin
                                                registers[`REG_A] <=
                                                        registers[`REG_A] & tmp;


@@ -614,11 +685,50 @@ module GBZ80Core(
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
                                                          registers[`REG_F][3:0]
                                                        };
                                        end

+                                       `INSN_alu_CP: begin
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b1,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end

                                        default:
                                                $stop;
                                        endcase
                                end
                        end
                                        default:
                                                $stop;
                                        endcase
                                end
                        end

+                       `INSN_ALU_A: begin
+                               case(opcode[5:3])
+                               `INSN_alu_RLCA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_RRCA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_RLA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_RRA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_CPL: begin
+                                       registers[`REG_A] <= ~registers[`REG_A];
+                                       registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
+                               end
+                               `INSN_alu_SCF: begin
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_CCF: begin
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
+                               end
+                               endcase
+                       end

                        `INSN_NOP: begin /* NOP! */ end
                        `INSN_RST: begin
                                case (cycle)
                        `INSN_NOP: begin /* NOP! */ end
                        `INSN_RST: begin
                                case (cycle)


@@ -656,6 +766,15 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

+                       `INSN_JP_imm,`INSN_JPCC_imm: begin
+                               case (cycle)
+                               0:      begin /* type F */ end
+                               1:      tmp <= rdata;   // tmp contains newpcl
+                               2:      tmp2 <= rdata;  // tmp2 contains newpch
+                               3:      {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                               {tmp2,tmp};
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -663,175 +782,3 @@ module GBZ80Core(
                end
                endcase
 endmodule
                end
                endcase
 endmodule

-
-`timescale 1ns / 1ps
-module ROM(
-       input [15:0] address,
-       inout [7:0] data,
-       input clk,
-       input wr, rd);
-
-       reg [7:0] rom [2047:0];
-       initial $readmemh("rom.hex", rom);
-
-       wire decode = address[15:13] == 0;
-       wire [7:0] odata = rom[address[11:0]];
-       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-       //assign data = rd ? odata : 8'bzzzzzzzz;
-endmodule
-
-module InternalRAM(
-       input [15:0] address,
-       inout [7:0] data,
-       input clk,
-       input wr, rd);
-       
-       reg [7:0] ram [8191:0];
-       
-       wire decode = (address >= 16'hC000) && (address < 16'hFE00);
-       reg [7:0] odata;
-       wire idata = data;
-       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-       
-       always @(negedge clk)
-       begin
-               if (decode && rd)
-                       odata <= ram[address[12:0]];
-               else if (decode && wr)
-                       ram[address[12:0]] <= data;
-       end
-endmodule
-
-module Switches(
-       input [15:0] address,
-       inout [7:0] data,
-       input clk,
-       input wr, rd,
-       input [7:0] switches,
-       output reg [7:0] ledout);
-       
-       wire decode = address == 16'hFF51;
-       reg [7:0] odata;
-       wire idata = data;
-       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
-       
-       always @(negedge clk)
-       begin
-               if (decode && rd)
-                       odata <= switches;
-               else if (decode && wr)
-                       ledout <= data;
-       end
-endmodule
-
-module CoreTop(
-       input xtal,
-       input [1:0] switches,
-       output wire [7:0] leds,
-       output serio,
-       output wire [3:0] digits,
-       output wire [7:0] seven);
-       
-       wire clk;
-       //IBUFG ibuf (.O(clk), .I(iclk));
-       
-       CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
-       wire [15:0] addr;
-       wire [7:0] data;
-       wire wr, rd;
-       
-       wire [7:0] ledout;
-       assign leds = switches[1] ? (switches[0]?{rd,wr,addr[5:0]}:data[7:0])
-                                               : ledout;
-
-       GBZ80Core core(
-               .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd));
-       
-       ROM rom(
-               .address(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd));
-       
-       AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven)
-    );
-        
-       Switches sw(
-               .address(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .ledout(ledout),
-               .switches(0)
-               );
-
-       UART nouart (
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
-endmodule
-
-module TestBench();
-       reg clk = 0;
-       wire [15:0] addr;
-       wire [7:0] data;
-       wire wr, rd;
-       
-//     wire [7:0] leds;
-//     wire [7:0] switches;
-       
-       always #10 clk <= ~clk;
-       GBZ80Core core(
-               .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd));
-       
-       ROM rom(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd));
-       
-//     InternalRAM ram(
-//             .address(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd));
-
-//     wire serio;
-//     UART uart(
-//             .addr(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd),
-//             .serial(serio));
-       
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
-endmodule