Start changing things to happen on posedge clock.

[fpgaboy.git] / Soundcore.v

diff --git a/Soundcore.v b/Soundcore.v
index 7752317f9e461e74f430c23cd7c37697a1146efd..626001ddd31b6050dec257a75372bb171a8baa35 100644 (file)
--- a/Soundcore.v
+++ b/Soundcore.v
@@ -36,7 +36,7 @@ module Soundcore(
                         addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(wr) begin
                        case(addr)
                        `ADDR_NR50: nr50 <= data;