Peripherals now have internal latches.

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index f9d71f4c17ef5bff177a5cd0a7b8dd0e3ce01f09..07f996a6a475add8a984a934271bba2c36f25b56 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -10,11 +10,12 @@ module UART(
        input [15:0] addr,
        inout [7:0] data,
        output reg serial = 1);
-       
+
+       reg rdlatch = 0;
        wire decode = (addr == `MMAP_ADDR);
        
        wire [7:0] odata;
-       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       assign data = rdlatch ? odata : 8'bzzzzzzzz;
 
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
@@ -27,6 +28,7 @@ module UART(
 
        always @ (posedge clk)
        begin
+               rdlatch <= rd && decode;
                /* deal with diqing */
                if(newdata) begin
                        data_stor <= data;