X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/74610a872e3bead82589e6ea786e928f319540e4..a8f4468d0cd6910eba8031e21038d76857a2c107:/Uart.v

diff --git a/Uart.v b/Uart.v
index f9d71f4..07f996a 100644
--- a/Uart.v
+++ b/Uart.v
@@ -10,11 +10,12 @@ module UART(
 	input [15:0] addr,
 	inout [7:0] data,
 	output reg serial = 1);
-	
+
+	reg rdlatch = 0;
 	wire decode = (addr == `MMAP_ADDR);
 	
 	wire [7:0] odata;
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 
 	reg [7:0] data_stor = 0;
 	reg [15:0] clkdiv = 0;
@@ -27,6 +28,7 @@ module UART(
 
 	always @ (posedge clk)
 	begin
+		rdlatch <= rd && decode;
 		/* deal with diqing */
 		if(newdata) begin
 			data_stor <= data;