call waitsw
- jp main
+ jr main
signon:
db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
ld [hli],a
ld a, $DF
cp h
- jp nz, .wr
+ jr nz, .wr
ld a, $80
cp l
- jp nz, .wr
+ jr nz, .wr
ld hl, $C000 ; Read loop
.rd:
ld b,a
ld a, [hli]
cp b
- jp nz, .memfail
+ jr nz, .memfail
ld a, $DF
cp h
- jp nz, .rd
+ jr nz, .rd
ld a, $80
cp l
- jp nz, .rd
+ jr nz, .rd
ld hl, testokstr ; Say we're OK
call puts
.loop1:
ld a,[c]
cp b
- jp z,.loop1
+ jr z,.loop1
.loop2:
ld a,[c]
cp b
- jp nz,.loop2
+ jr nz,.loop2
ret
waitswstr:
ld hl, .pushpopfail
ld a, d
cp b
- jp nz,.fail
+ jr nz,.fail
ld a, e
cp c
- jp nz,.fail
+ jr nz,.fail
; Test ALU (HL).
ld hl, .ff
ld a, $FF
xor [hl]
ld hl, .xorhlfail
- jp nz, .fail
+ jr nz, .fail
; Test JP (HL)
ld hl, .jphl
jp [hl]
ld hl, .jphlfail
- jp .fail
+ jr .fail
rst $00
.jphl:
cp b
jr nz,.jr
ld hl, .jrfail
- jp .fail
+ jr .fail
rst $00
.jr:
ld a, $10
ld b, $20
cp b
- jp nc,.fail
+ jr nc,.fail
ld a, $20
ld b, $10
cp b
- jp c,.fail
+ jr c,.fail
; Test CPL
ld hl, .cplfail
ld b, $AA
cpl
cp b
- jp nz,.fail
+ jr nz,.fail
ld hl, .ok
call puts
.waitport:
ld a,[c]
cp b
- jp nz,.waitport
+ jr nz,.waitport
pop af
ld [c],a
ret
ld a, [hli]
ld b, $00
cp b
- jp z, .done
+ jr z, .done
call putc
- jp puts
+ jr puts
.done:
ret